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Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1wD1EC-00000001Eha-02cW; Wed, 15 Apr 2026 14:28:28 +0000 Received: from sea.source.kernel.org ([2600:3c0a:e001:78e:0:1991:8:25]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1wD1E9-00000001EhF-1Gm9 for linux-riscv@lists.infradead.org; Wed, 15 Apr 2026 14:28:26 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sea.source.kernel.org (Postfix) with ESMTP id 240FC42D6B; Wed, 15 Apr 2026 14:28:24 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id B35EBC19424; Wed, 15 Apr 2026 14:28:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1776263304; bh=KLZl5mWnQ/fLEg517Nj8h/rm6MAMa8dENX79Fq95dso=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=H/YX+RVRFmDbZUEUouHLuZhFFOhEriVotbvOFw9wxSIAFOu1yin3oKr9hQA0Qc6pR I+WFVtfV4rosaPXwqeX+Kw27EcgVj1wXrS3hkWJI6FDy6VzZ/VM4FeseN1YJUcOtKF cIcgd6P3ftw6wMwBFE9Y5dT8LLZ8beEgm4Maazw7DT9d8U/b5MKbcLdDahzLWTvnq8 y/Ia9YUWY2hscVdDJP/lLNEJaYQz2XQGSMPfrI7GvlevKVswmJ/nF5Bl8wOzaYMnE3 3DB6G88J25UbvGy8+m0Peq0i8FqFF4fMf3+qxz5TJSxVacU/syZf5Hlb4HhAvCdLsO GpYzCyeW8yc9A== Date: Wed, 15 Apr 2026 15:28:18 +0100 From: Conor Dooley To: Jia Wang Cc: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Jingoo Han , Xincheng Zhang , Krzysztof Kozlowski , Conor Dooley , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH v3 1/3] riscv: add UltraRISC SoC family Kconfig support Message-ID: <20260415-craving-rubbing-bc8d389d19de@spud> References: <20260415-ultrarisc-pcie-v3-0-73f06e972616@ultrarisc.com> <20260415-ultrarisc-pcie-v3-1-73f06e972616@ultrarisc.com> MIME-Version: 1.0 In-Reply-To: <20260415-ultrarisc-pcie-v3-1-73f06e972616@ultrarisc.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260415_072825_384671_CE31792F X-CRM114-Status: GOOD ( 15.52 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: multipart/mixed; boundary="===============3739132551671547765==" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org --===============3739132551671547765== Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="m8S0HS9rYZzLUqT+" Content-Disposition: inline --m8S0HS9rYZzLUqT+ Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Wed, Apr 15, 2026 at 03:21:17PM +0800, Jia Wang wrote: > The first SoC in the UltraRISC series is UR-DP1000, containing octa > UltraRISC CP100 cores. >=20 > Signed-off-by: Jia Wang Acked-by: Conor Dooley > --- > arch/riscv/Kconfig.socs | 6 ++++++ > 1 file changed, 6 insertions(+) >=20 > diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs > index d621b85dd63b..0b4d06a7b4bf 100644 > --- a/arch/riscv/Kconfig.socs > +++ b/arch/riscv/Kconfig.socs > @@ -84,6 +84,12 @@ config ARCH_THEAD > help > This enables support for the RISC-V based T-HEAD SoCs. > =20 > +config ARCH_ULTRARISC > + bool "UltraRISC RISC-V SoCs" > + help > + This enables support for UltraRISC SoC platform hardware, > + including boards based on the UR-DP1000. > + > config ARCH_VIRT > bool "QEMU Virt Machine" > select POWER_RESET >=20 > --=20 > 2.34.1 >=20 --m8S0HS9rYZzLUqT+ Content-Type: application/pgp-signature; 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