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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The StarFive JH8100 SoC was discontinued before production. The newly taped-out JHB100 SoC uses the same interrupt controller IP. Rename the binding file, compatible string, and MAINTAINERS entry from "jh8100" to "jhb100". In JHB100 SoC, The clocks and resets are not operated by users, but they exist in the hardware. Mark them as optional. Signed-off-by: Changhuang Liang Acked-by: Conor Dooley --- ...00-intc.yaml => starfive,jhb100-intc.yaml} | 20 ++++--------------- MAINTAINERS | 2 +- 2 files changed, 5 insertions(+), 17 deletions(-) rename Documentation/devicetree/bindings/interrupt-controller/{starfive,jh8100-intc.yaml => starfive,jhb100-intc.yaml} (68%) diff --git a/Documentation/devicetree/bindings/interrupt-controller/starfive,jh8100-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/starfive,jhb100-intc.yaml similarity index 68% rename from Documentation/devicetree/bindings/interrupt-controller/starfive,jh8100-intc.yaml rename to Documentation/devicetree/bindings/interrupt-controller/starfive,jhb100-intc.yaml index ada5788602d6..d8a0a3862ae2 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/starfive,jh8100-intc.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/starfive,jhb100-intc.yaml @@ -1,13 +1,13 @@ # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause %YAML 1.2 --- -$id: http://devicetree.org/schemas/interrupt-controller/starfive,jh8100-intc.yaml# +$id: http://devicetree.org/schemas/interrupt-controller/starfive,jhb100-intc.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: StarFive External Interrupt Controller description: - StarFive SoC JH8100 contain a external interrupt controller. It can be used + StarFive SoC JHB100 contain a external interrupt controller. It can be used to handle high-level input interrupt signals. It also send the output interrupt signal to RISC-V PLIC. @@ -16,19 +16,11 @@ maintainers: properties: compatible: - const: starfive,jh8100-intc + const: starfive,jhb100-intc reg: maxItems: 1 - clocks: - description: APB clock for the interrupt controller - maxItems: 1 - - resets: - description: APB reset for the interrupt controller - maxItems: 1 - interrupts: maxItems: 1 @@ -40,8 +32,6 @@ properties: required: - compatible - reg - - clocks - - resets - interrupts - interrupt-controller - "#interrupt-cells" @@ -51,10 +41,8 @@ additionalProperties: false examples: - | interrupt-controller@12260000 { - compatible = "starfive,jh8100-intc"; + compatible = "starfive,jhb100-intc"; reg = <0x12260000 0x10000>; - clocks = <&syscrg_ne 76>; - resets = <&syscrg_ne 13>; interrupts = <45>; interrupt-controller; #interrupt-cells = <1>; diff --git a/MAINTAINERS b/MAINTAINERS index d238590a31f2..a2961727e3d1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -25312,7 +25312,7 @@ F: drivers/phy/starfive/phy-jh7110-usb.c STARFIVE JH8100 EXTERNAL INTERRUPT CONTROLLER DRIVER M: Changhuang Liang S: Supported -F: Documentation/devicetree/bindings/interrupt-controller/starfive,jh8100-intc.yaml +F: Documentation/devicetree/bindings/interrupt-controller/starfive,jhb100-intc.yaml F: drivers/irqchip/irq-starfive-jh8100-intc.c STATIC BRANCH/CALL -- 2.25.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv