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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Wed, Apr 15, 2026 at 05:38:27PM +0800, Jinjie Ruan wrote: > The RISC-V Bit-manipulation Extension for Cryptography (Zbkb) provides > the 'brev8' instruction, which reverses the bits within each byte. > Combined with the 'rev8' instruction (from Zbb or Zbkb), which reverses > the byte order of a register, we can efficiently implement 16-bit, > 32-bit, and (on RV64) 64-bit bit reversal. > > This is significantly faster than the default software table-lookup > implementation in lib/bitrev.c, as it replaces memory accesses and > multiple arithmetic operations with just two or three hardware > instructions. > > Select HAVE_ARCH_BITREVERSE and provide to utilize > these instructions when the Zbkb extension is available at runtime > via the alternatives mechanism. > > Signed-off-by: Jinjie Ruan > --- > arch/riscv/Kconfig | 1 + > arch/riscv/include/asm/bitrev.h | 41 +++++++++++++++++++++++++++++++++ > 2 files changed, 42 insertions(+) > create mode 100644 arch/riscv/include/asm/bitrev.h > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > index 90c531e6abf5..05f2b2166a83 100644 > --- a/arch/riscv/Kconfig > +++ b/arch/riscv/Kconfig > @@ -128,6 +128,7 @@ config RISCV > select HAS_IOPORT if MMU > select HAVE_ALIGNED_STRUCT_PAGE > select HAVE_ARCH_AUDITSYSCALL > + select HAVE_ARCH_BITREVERSE if RISCV_ISA_ZBKB > select HAVE_ARCH_HUGE_VMALLOC if HAVE_ARCH_HUGE_VMAP > select HAVE_ARCH_HUGE_VMAP if MMU && 64BIT > select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL > diff --git a/arch/riscv/include/asm/bitrev.h b/arch/riscv/include/asm/bitrev.h > new file mode 100644 > index 000000000000..9f205ac84796 > --- /dev/null > +++ b/arch/riscv/include/asm/bitrev.h > @@ -0,0 +1,41 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +#ifndef __ASM_BITREV_H > +#define __ASM_BITREV_H > + > +#include > +#include > +#include > +#include > + > +static __always_inline __attribute_const__ u32 __arch_bitrev32(u32 x) > +{ > + unsigned long result = x; > + > + if (!riscv_has_extension_likely(RISCV_ISA_EXT_ZBKB)) > + return generic___bitrev32(x); This breaks the build when CONFIG_HAVE_ARCH_BITREVERSE is set because generic___bitrev32() ultimately calls generic___bitrev8(), which uses byte_rev_table but that is only included in lib/bitrev.c when CONFIG_HAVE_ARCH_BITREVERSE is not set. How was this tested? This seems a pretty basic build problem that has showed up in a variety of configurations (at least all the configurations that our CI tests). $ make -skj"$(nproc)" ARCH=riscv CROSS_COMPILE=riscv64-linux- mrproper defconfig all ERROR: modpost: "byte_rev_table" [lib/zlib_deflate/zlib_deflate.ko] undefined! ERROR: modpost: "byte_rev_table" [drivers/net/ethernet/spacemit/k1_emac.ko] undefined! ERROR: modpost: "byte_rev_table" [drivers/net/ethernet/stmicro/stmmac/stmmac.ko] undefined! https://github.com/ClangBuiltLinux/continuous-integration2/actions/runs/24529356842 https://lore.kernel.org/177635154368.6552.7060101263009785041@8692ffc4d55e/ Yury, are you intending to send this series to Linus in the 7.1 merge window? If not, it shouldn't be in -next at this point. > + asm volatile( > + ".option push\n" > + ".option arch,+zbkb\n" > + "rev8 %0, %0\n" > + "brev8 %0, %0\n" > + ".option pop" > + : "+r" (result) > + ); > + > + if (__riscv_xlen == 64) > + return (u32)(result >> 32); > + > + return (u32)result; > +} > + > +static __always_inline __attribute_const__ u16 __arch_bitrev16(u16 x) > +{ > + return __arch_bitrev32((u32)x) >> 16; > +} > + > +static __always_inline __attribute_const__ u8 __arch_bitrev8(u8 x) > +{ > + return __arch_bitrev32((u32)x) >> 24; > +} > +#endif > -- > 2.34.1 > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv