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[82.69.66.36]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-488fc1c01cfsm68401345e9.10.2026.04.17.11.43.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Apr 2026 11:43:00 -0700 (PDT) Date: Fri, 17 Apr 2026 19:42:59 +0100 From: David Laight To: Yury Norov Cc: Jinjie Ruan , pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, yury.norov@gmail.com, linux@rasmusvillemoes.dk, arnd@arndb.de, akpm@linux-foundation.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org, nathan@kernel.org Subject: Re: [PATCH v3 0/2] arch/riscv: Add bitrev.h file to support rev8 and brev8 Message-ID: <20260417194259.0c48d7ef@pumpkin> In-Reply-To: References: <20260417093102.3812978-1-ruanjinjie@huawei.com> X-Mailer: Claws Mail 4.1.1 (GTK 3.24.38; arm-unknown-linux-gnueabihf) MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260417_114303_718620_B9D4EA88 X-CRM114-Status: GOOD ( 17.15 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Fri, 17 Apr 2026 12:09:03 -0400 Yury Norov wrote: > On Fri, Apr 17, 2026 at 05:31:00PM +0800, Jinjie Ruan wrote: > > Add bitrev.h file to support rev8 and brev8 for riscv. > > > > Tested functionally on riscv64 QEMU with: > > "-M virt,acpi=on,zbkb=true,zbb=true" > > > > Changes in v3: > > - Fix the build issue by remving the CONFIG_HAVE_ARCH_BITREVERSE macro > > for byte_rev_table. > > No arch needs byte_rev_table, except risc-v under a very certain > configuration. Please find a better approach that wouldn't bloat > random victims' .data section. Eh? x86 doesn't have a bit-reverse instruction. The only arch that 'select HAVE_ARCH_BITREVERSE' are arm64, arm32 (some cpu), loongarch and mips (for CPU_MIPSR6). I think you mean that no arch that sets CONFIG_HAVE_ARCH_BITREVERSE needs it except riscv. Could you globally have: select NEED_BYTE_REV_TABLE if !HAVE_ARCH_BITREVERSE and then riscv could also select it? (And isn't there a method of including files in the build based on kconfig options rather than unconditionally compiling it and getting cpp to throw the contents away?) David > > > - Update the riscv implementation as David suggested. > > - Add Reviwed-by. > > > > Changes in v2: > > - Define generic __bitrev8/16/32 for reuse in riscv. > > > > Jinjie Ruan (2): > > bitops: Define generic __bitrev8/16/32 for reuse > > arch/riscv: Add bitrev.h file to support rev8 and brev8 > > > > arch/riscv/Kconfig | 1 + > > arch/riscv/include/asm/bitrev.h | 55 +++++++++++++++++++++++++++ > > include/asm-generic/bitops/__bitrev.h | 22 +++++++++++ > > include/linux/bitrev.h | 20 ++-------- > > lib/bitrev.c | 3 -- > > 5 files changed, 82 insertions(+), 19 deletions(-) > > create mode 100644 arch/riscv/include/asm/bitrev.h > > create mode 100644 include/asm-generic/bitops/__bitrev.h > > > > -- > > 2.34.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv