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X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org >> From: Fangyu Yu >> >> When mapping writable pages, the RISC-V format code currently >> pre-sets the PTE D bit unconditionally. >> >> If hardware dirty tracking is active (DC.tc.GADE set), the IOMMU >> sets D autonomously on the first write. Pre-setting D makes every >> new mapping appear dirty immediately and breaks dirty tracking. >> >> Introduce PT_FEAT_RISCV_DIRTY_TRACKING_ACTIVE and, when set, leave >> D cleared for new writable mappings so hardware can capture the >> first write. Keep pre-setting D when dirty tracking is inactive. >> >> Only meaningful for second-stage (iohgatp) page tables. > >You shouldn't need anything like this, the D bit is managed by the >iommufd core appropriately. It *should* start out pre-set as that is >faster when not tacking. Only once dirty tracking is started does D >get cleared. User space is supposed to assume that everything is dirty >prior to its first D clear. > Thanks, that makes sense. I will drop PT_FEAT_RISCV_DIRTY_TRACKING_ACTIVE and rely on the iommufd core to manage D bit. Fangyu >Jason _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv