From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 33DEFCD37A9 for ; Thu, 7 May 2026 11:37:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=65mrUYOq1AsQT/b89/JDHC6sf6N9d0AwsGBUgPbtu8c=; b=K9DZzTGhhkND9K 8ECnftQdeTUkbD2Bok2SGGKAqFc3aVqSYIHsLcRBN8MAFqcD5g7TVSCrxX7Q/UcK7rLfi2IfAMjpz bUJ1w70Pyu8fE6aor1On+TL+UqRPmyXB9MGnTEyAsgsAEw0N4ogHn9bF6rQ/cGwCT944Y/imd+GT1 u+S8NJhU9ChQ+58+FT32tHLsFlmrZNgJo3wbFIJdJ1ERO+PwyE2HLhFhd8Cs3g+eeuKaO1tPules7 1buU5Lt06mTCRPUJO0RBER7ODCUUDHdfBFRD00K7mXRf66SUQzkpHcmVPbdaMfYpc7MPi+hfvgZcr 3JsA2gLdVnKTB3b4L+kQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.99.1 #2 (Red Hat Linux)) id 1wKx2t-00000003end-0DKn; Thu, 07 May 2026 11:37:35 +0000 Received: from out30-98.freemail.mail.aliyun.com ([115.124.30.98]) by bombadil.infradead.org with esmtps (Exim 4.99.1 #2 (Red Hat Linux)) id 1wKx2p-00000003ehf-3CG6; Thu, 07 May 2026 11:37:33 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1778153849; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=ymvPBhIqjH6VI2cF6B82ob0998YC79NL7DciLWQChAk=; b=dUNgbBRO9bSMtaUG0fStJ5qFh509/7KbQpyt6mZksHhscr+wiF/dQfBSuFupao4iS+fsncOVNlvIPQ3J4hEBZ16XC1zpBKTfEzs6S01gWcYFASXEP0oGZ+dpOafEKA3qYcDzWWrAYnmy7q9wc1fpnSLp7scIJCzr53KvzbvNpV4= X-Alimail-AntiSpam: AC=PASS;BC=-1|-1;BR=01201311R101e4;CH=green;DM=||false|;DS=||;FP=0|-1|-1|-1|0|-1|-1|-1;HT=maildocker-contentspam033037033178;MF=fangyu.yu@linux.alibaba.com;NM=1;PH=DS;RN=24;SR=0;TI=SMTPD_---0X2UVF2E_1778153843; Received: from localhost.localdomain(mailfrom:fangyu.yu@linux.alibaba.com fp:SMTPD_---0X2UVF2E_1778153843 cluster:ay36) by smtp.aliyun-inc.com; Thu, 07 May 2026 19:37:24 +0800 From: fangyu.yu@linux.alibaba.com To: joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, tjeznach@rivosinc.com, jgg@ziepe.ca, kevin.tian@intel.com, baolu.lu@linux.intel.com, vasant.hegde@amd.com, anup@brainfault.org, atish.patra@linux.dev, skhawaja@google.com, jgg@nvidia.com Cc: guoren@kernel.org, andrew.jones@oss.qualcomm.com, kvm@vger.kernel.org, iommu@lists.linux.dev, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Fangyu Yu Subject: [RFC PATCH v2 09/10] iommu/riscv: Add dirty tracking support for second-stage domains Date: Thu, 7 May 2026 19:37:05 +0800 Message-Id: <20260507113706.11400-10-fangyu.yu@linux.alibaba.com> X-Mailer: git-send-email 2.39.3 (Apple Git-146) In-Reply-To: <20260507113706.11400-1-fangyu.yu@linux.alibaba.com> References: <20260507113706.11400-1-fangyu.yu@linux.alibaba.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260507_043732_154984_F8385525 X-CRM114-Status: GOOD ( 10.23 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Fangyu Yu Add hardware dirty tracking support for second-stage (iohgatp) domains used in KVM VFIO device pass-through. The RISC-V IOMMU can automatically set the dirty bit in PTEs on write access when DC.tc.GADE is set and the hardware has AMO_HWAD capability. Wire this up to the iommufd dirty tracking interface: - riscv_iommu_set_dirty_tracking(): Always enabled dirty tracking for second-stage domain. - riscv_iommu_dirty_ops: Exposes set_dirty_tracking and the generic page-table read_and_clear_dirty via IOMMU_PT_DIRTY_OPS(riscv_64). - domain_alloc_paging_flags: Assigns dirty_ops to second-stage domains when AMO_HWAD is advertised in hardware capabilities. - riscv_iommu_capable: Reports IOMMU_CAP_DIRTY_TRACKING when AMO_HWAD is present. Signed-off-by: Fangyu Yu --- drivers/iommu/riscv/iommu.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c index 4adf2b6be89b..b7944149dcfe 100644 --- a/drivers/iommu/riscv/iommu.c +++ b/drivers/iommu/riscv/iommu.c @@ -1249,6 +1249,21 @@ static int riscv_iommu_attach_paging_domain(struct iommu_domain *iommu_domain, return 0; } +static int riscv_iommu_set_dirty_tracking(struct iommu_domain *iommu_domain, + bool enable) +{ + /* + * Always enabled and the dirty bitmap is cleared prior to + * set_dirty_tracking(). + */ + return 0; +} + +static const struct iommu_dirty_ops riscv_iommu_dirty_ops = { + IOMMU_PT_DIRTY_OPS(riscv_64), + .set_dirty_tracking = riscv_iommu_set_dirty_tracking, +}; + static const struct iommu_domain_ops riscv_iommu_paging_domain_ops = { IOMMU_PT_DOMAIN_OPS(riscv_64), .attach_dev = riscv_iommu_attach_paging_domain, @@ -1336,6 +1351,8 @@ static struct iommu_domain *riscv_iommu_domain_alloc_paging_flags( goto err_free; } cfg.common.features |= BIT(PT_FEAT_RISCV_S2); + if (iommu->caps & RISCV_IOMMU_CAPABILITIES_AMO_HWAD) + domain->domain.dirty_ops = &riscv_iommu_dirty_ops; break; default: ret = -EOPNOTSUPP; @@ -1411,9 +1428,13 @@ static struct iommu_group *riscv_iommu_device_group(struct device *dev) static bool riscv_iommu_capable(struct device *dev, enum iommu_cap cap) { + struct riscv_iommu_device *iommu = dev_to_iommu(dev); + switch (cap) { case IOMMU_CAP_CACHE_COHERENCY: return true; + case IOMMU_CAP_DIRTY_TRACKING: + return !!(iommu->caps & RISCV_IOMMU_CAPABILITIES_AMO_HWAD); default: return false; } -- 2.50.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv