From: Zishun Yi <vulab@iscas.ac.cn>
To: Anup Patel <anup@brainfault.org>, Paul Walmsley <pjw@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>
Cc: Atish Patra <atish.patra@linux.dev>,
Alexandre Ghiti <alex@ghiti.fr>,
Andrew Jones <ajones@ventanamicro.com>,
kvm@vger.kernel.org, kvm-riscv@lists.infradead.org,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
Zishun Yi <vulab@iscas.ac.cn>
Subject: [PATCH] riscv: KVM: Fix missing TLB flush on HENVCFG.PMM updates
Date: Sat, 9 May 2026 19:41:22 +0800 [thread overview]
Message-ID: <20260509114122.1868327-1-vulab@iscas.ac.cn> (raw)
According to the RISC-V Privileged ISA specification, if henvcfg.PMM is
changed from or to a value where (XLEN-PMLEN) is less than the GPA width
supported by the hgatp translation mode of that guest, hypervisors must
execute an HFENCE.GVMA with rs1=x0.
Currently, when a guest dynamically changes pointer masking mode via the
SBI FWFT extension, kvm_sbi_fwft_set_pointer_masking_pmlen() directly
modifies the hardware CSR_HENVCFG from the non-one-reg-access path
without issuing the required TLB invalidation
Fix this by adding an unconditional HFENCE.GVMA after the CSR write.
This vulnerability was discovered and reported by my SpecHunter, an
AI-driven architecture specification analysis tool.
Link: https://github.com/yizishun/rv-isa-sec/blob/master/output/riscv-isa-manual/pr-2494/linux.txt
Fixes: 48d67106f4a7 ("RISC-V: KVM: Implement ONE_REG interface for SBI FWFT state")
Assisted-by: DeepSeek:DeepSeek-V4-Pro
Signed-off-by: Zishun Yi <vulab@iscas.ac.cn>
---
arch/riscv/kvm/vcpu_sbi_fwft.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/kvm/vcpu_sbi_fwft.c b/arch/riscv/kvm/vcpu_sbi_fwft.c
index 2eab15339694..c2bd3ae699fd 100644
--- a/arch/riscv/kvm/vcpu_sbi_fwft.c
+++ b/arch/riscv/kvm/vcpu_sbi_fwft.c
@@ -186,8 +186,10 @@ static long kvm_sbi_fwft_set_pointer_masking_pmlen(struct kvm_vcpu *vcpu,
* update here so that VCPU see's pointer masking mode change
* immediately.
*/
- if (!one_reg_access)
+ if (!one_reg_access) {
csr_write(CSR_HENVCFG, vcpu->arch.cfg.henvcfg);
+ kvm_riscv_local_hfence_gvma_all();
+ }
return SBI_SUCCESS;
}
--
2.51.2
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
reply other threads:[~2026-05-09 11:42 UTC|newest]
Thread overview: [no followups] expand[flat|nested] mbox.gz Atom feed
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20260509114122.1868327-1-vulab@iscas.ac.cn \
--to=vulab@iscas.ac.cn \
--cc=ajones@ventanamicro.com \
--cc=alex@ghiti.fr \
--cc=anup@brainfault.org \
--cc=aou@eecs.berkeley.edu \
--cc=atish.patra@linux.dev \
--cc=kvm-riscv@lists.infradead.org \
--cc=kvm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=palmer@dabbelt.com \
--cc=pjw@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox