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Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.99.1 #2 (Red Hat Linux)) id 1wMr3y-0000000HZ99-2DyP; Tue, 12 May 2026 17:38:34 +0000 Received: from sea.source.kernel.org ([2600:3c0a:e001:78e:0:1991:8:25]) by bombadil.infradead.org with esmtps (Exim 4.99.1 #2 (Red Hat Linux)) id 1wMr3v-0000000HZ8g-3S1t for linux-riscv@lists.infradead.org; Tue, 12 May 2026 17:38:33 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sea.source.kernel.org (Postfix) with ESMTP id 2B0B540BF3; Tue, 12 May 2026 17:38:31 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 18981C2BCB0; Tue, 12 May 2026 17:38:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1778607511; bh=Lh4wZ2wxbXrL/PMypQSELTSMyjIJKr5egJCQ3MixpNs=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=nBhAfbh/Rz/3sOchPEJ7316+gfWx8Zlpfpur8Va/rByCxc3VKBhfXd09EcGAiDstx 33B208k8iVJPVyVYzgqD3z0GEBEaNgeo8i8o8ISr5bQ3V00uWqf0I0YNi44RiWc4H6 r1wY0DPFN4qllsDpjRAuEH8YyCV8fsHFHfRCEeA2IvZXo8LKNTp8o8pdaRQw2m8+VT r7PG6CUQdOMJBU99axUJZJr41QWnSiRLqaFa79yj+Qgl+x/FqW8bxJjdxtV65iuwmC r+z1fRRTSbaBezAXTEodCEfu6+YERtuKB5fWlLpbRFVwth8U5SrcnQIJbyw4PMPaJm OxUwwl1S+hrMw== Date: Tue, 12 May 2026 18:38:24 +0100 From: Conor Dooley To: Changhuang Liang Cc: Michael Turquette , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Stephen Boyd , Brian Masney , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Philipp Zabel , Emil Renner Berthing , Chen Wang , Inochi Amaoto , Alexey Charkov , Thomas Bogendoerfer , Keguang Zhang , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org Subject: Re: [PATCH v2 01/12] dt-bindings: soc: starfive: Add StarFive JHB100 syscon modules Message-ID: <20260512-operator-vindicate-339bf407d7f3@spud> References: <20260512083521.3448-1-changhuang.liang@starfivetech.com> <20260512083521.3448-2-changhuang.liang@starfivetech.com> MIME-Version: 1.0 In-Reply-To: <20260512083521.3448-2-changhuang.liang@starfivetech.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260512_103831_906085_AB0662D4 X-CRM114-Status: GOOD ( 18.29 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: multipart/mixed; boundary="===============6070000831065580534==" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org --===============6070000831065580534== Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="e5f+9DcEecnTfzlC" Content-Disposition: inline --e5f+9DcEecnTfzlC Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Tue, May 12, 2026 at 01:35:10AM -0700, Changhuang Liang wrote: > Add documentation to describe StarFive JHB100 SoC System Controller > Registers. >=20 > Signed-off-by: Changhuang Liang > --- > .../soc/starfive/starfive,jhb100-syscon.yaml | 107 ++++++++++++++++++ > MAINTAINERS | 5 + > 2 files changed, 112 insertions(+) > create mode 100644 Documentation/devicetree/bindings/soc/starfive/starfi= ve,jhb100-syscon.yaml >=20 > diff --git a/Documentation/devicetree/bindings/soc/starfive/starfive,jhb1= 00-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/starfive,jh= b100-syscon.yaml > new file mode 100644 > index 000000000000..0add3d9727ac > --- /dev/null > +++ b/Documentation/devicetree/bindings/soc/starfive/starfive,jhb100-sysc= on.yaml > @@ -0,0 +1,107 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/soc/starfive/starfive,jhb100-syscon.y= aml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: StarFive JHB100 SoC system controller > + > +maintainers: > + - Kevin Xie > + - Changhuang Liang > + > +description: > + The StarFive JHB100 SoC system controller contains MMIO registers used= by > + other hardware modules (e.g., PLL, eMMC, PCIe). These modules access > + specific register offsets, bit masks, and shifts within the system > + controller region for configuration and status. > + > +properties: > + compatible: > + items: > + - enum: > + - starfive,jhb100-b2h-syscon > + - starfive,jhb100-gpu-syscon > + - starfive,jhb100-h2b-syscon > + - starfive,jhb100-host-syscon > + - starfive,jhb100-husb-syscon > + - starfive,jhb100-husbcmn-syscon > + - starfive,jhb100-husbd-syscon > + - starfive,jhb100-npu-syscon > + - starfive,jhb100-pcieep-ecsr-syscon > + - starfive,jhb100-pcierp-ecsr-syscon > + - starfive,jhb100-pcierp-syscon > + - starfive,jhb100-per0-syscon > + - starfive,jhb100-per1-syscon > + - starfive,jhb100-per2-syscon > + - starfive,jhb100-per3-syscon > + - starfive,jhb100-strap-syscon > + - starfive,jhb100-sys0-syscon > + - starfive,jhb100-sys1-syscon > + - starfive,jhb100-sys2-syscon > + - starfive,jhb100-usb-syscon > + - starfive,jhb100-vout-syscon > + - const: syscon > + > + reg: > + maxItems: 1 > + > + clocks: > + maxItems: 1 > + > + '#clock-cells': > + const: 1 > + > + '#reset-cells': > + const: 1 > + > +required: > + - compatible > + - reg > + > +allOf: > + - if: > + properties: > + compatible: > + contains: > + enum: > + - starfive,jhb100-per0-syscon > + - starfive,jhb100-per1-syscon > + - starfive,jhb100-sys0-syscon > + then: > + required: > + - clocks > + - '#clock-cells' Probably missing and else: clocks/clock-cells: false? And the same below for resets? > + > + - if: > + properties: > + compatible: > + contains: > + const: starfive,jhb100-pcierp-syscon > + then: > + required: > + - '#reset-cells' > + > +additionalProperties: false > + > +examples: > + - | > + syscon@13010000 { > + compatible =3D "starfive,jhb100-sys0-syscon", "syscon"; > + reg =3D <0x13010000 0x2000>; > + clocks =3D <&osc>; > + #clock-cells =3D <1>; > + }; > + > + syscon@13014000 { > + compatible =3D "starfive,jhb100-sys1-syscon", "syscon"; > + reg =3D <0x13014000 0x4000>; > + }; > + > + syscon@11719000 { > + compatible =3D "starfive,jhb100-pcierp-syscon", "syscon"; > + reg =3D <0x11719000 0x1000>; > + #reset-cells =3D <1>; > + }; > + > +... > diff --git a/MAINTAINERS b/MAINTAINERS > index 47e4b368347f..6f6aac7cea95 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -25613,6 +25613,11 @@ S: Maintained > F: drivers/reset/starfive/reset-starfive-jhb1* > F: include/dt-bindings/reset/starfive,jhb1*.h > =20 > +STARFIVE JHB100 SYSCON > +M: Changhuang Liang > +S: Maintained > +F: Documentation/devicetree/bindings/soc/starfive/starfive,jhb100-syscon= =2Eyaml > + > STATIC BRANCH/CALL > M: Peter Zijlstra > M: Josh Poimboeuf > --=20 > 2.25.1 >=20 --e5f+9DcEecnTfzlC Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYKAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCagNlkAAKCRB4tDGHoIJi 0osyAP9nG5LpF/CsWXBrsbCldev1ga7IWfs9Nuw6cCVorDxtlwD8Da2mhdujsZzD dWkYJ8EY0O5iSm8tU81TxPJeGAoIHwQ= =/WCt -----END PGP SIGNATURE----- --e5f+9DcEecnTfzlC-- --===============6070000831065580534== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv --===============6070000831065580534==--