Re: [PATCH 1/2] riscv: track effective hardware PTE A/D updates

From: Conor Dooley <conor@kernel.org>
To: Samuel Holland <samuel.holland@sifive.com>
Cc: Michael Ellerman <mpe@kernel.org>,
	Yunhui Cui <cuiyunhui@bytedance.com>,
	pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu,
	alex@ghiti.fr, akpm@linux-foundation.org,
	pasha.tatashin@soleen.com, andrew+kernel@donnellan.id.au,
	rmclure@linux.ibm.com, debug@rivosinc.com,
	baolin.wang@linux.alibaba.com, zhangchunyan@iscas.ac.cn,
	apopple@nvidia.com, namcao@linutronix.de,
	wangruikang@iscas.ac.cn, apatel@ventanamicro.com,
	liu.xuemei1@zte.com.cn, ajones@ventanamicro.com,
	cleger@rivosinc.com, charlie@rivosinc.com,
	hui.wang@canonical.com, guodong@riscstar.com,
	pincheng.plct@isrc.iscas.ac.cn, linux-riscv@lists.infradead.org,
	linux-kernel@vger.kernel.org,
	Qingwei Hu <qingwei.hu@bytedance.com>
Subject: Re: [PATCH 1/2] riscv: track effective hardware PTE A/D updates
Date: Tue, 19 May 2026 20:40:23 +0100	[thread overview]
Message-ID: <20260519-uniformly-italicize-7559af43864a@spud> (raw)
In-Reply-To: <66c1503a-5fc5-432d-8312-403b2999d9d4@sifive.com>


[-- Attachment #1.1: Type: text/plain, Size: 1877 bytes --]

On Tue, May 19, 2026 at 12:34:44PM -0500, Samuel Holland wrote:

> >>> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> >>> index f46aa5602d74d..e46b2d2b49eed 100644
> >>> --- a/arch/riscv/kernel/cpufeature.c
> >>> +++ b/arch/riscv/kernel/cpufeature.c
> >>> @@ -35,6 +35,8 @@
> >>>   static bool any_cpu_has_zicboz;
> >>>   static bool any_cpu_has_zicbop;
> >>>   static bool any_cpu_has_zicbom;
> >>> +bool riscv_hw_pte_ad_updating_enabled __read_mostly;
> >>> +EXPORT_SYMBOL_GPL(riscv_hw_pte_ad_updating_enabled);
> >>>   unsigned long elf_hwcap __read_mostly;
> >>> @@ -287,15 +289,74 @@ static int riscv_ext_zvfbfwma_validate(const struct riscv_isa_ext_data *data,
> >> ...
> >>> +static int __init riscv_hw_pte_ad_updating_init(void)
> >>> +{
> >>> +	bool has_svade, has_svadu;
> >>> +	int state;
> >>> +
> >>> +	has_svade = riscv_has_extension_unlikely(RISCV_ISA_EXT_SVADE);
> >>> +	has_svadu = riscv_has_extension_unlikely(RISCV_ISA_EXT_SVADU);
> >>> +
> >>> +	if (!has_svadu)
> >>> +		return 0;
> >>> +
> >>> +	if (!has_svade) {
> >>> +		riscv_set_hw_pte_ad_updating(true);
> >>> +		pr_info("riscv: hardware PTE A/D updating enabled\n");
> >>> +		return 0;
> >>
> >> This block is identical to the tail of the function. I'd probably use "goto
> >> enable", with an "enable" label below.
> > 
> > Is this code correct though? On DT systems, !svade && !svadu means we
> > don't actually know if it is hardware or software managed, so printing
> > that it's hardware managed may not be correct.
> > 
> > I don't understand the mm code enough to know if arch_has_hw_pte_young()
> > returning true is problematic too, but it probably is?
> 
> This block is for !svade && svadu (Svadu is present; we didn't return above), so
> I think this block and Michael's comment are correct.

D'oh... My bad!


[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

[-- Attachment #2: Type: text/plain, Size: 161 bytes --]

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv