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[9.244.8.156]) by smtp.gmail.com with ESMTPSA id af79cd13be357-92e80194291sm274217585a.37.2026.07.02.11.11.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jul 2026 11:11:43 -0700 (PDT) From: Enzo Adriano To: Junhui Liu Cc: Andre Przywara , Brian Masney , Michael Turquette , Stephen Boyd , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Philipp Zabel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Richard Cochran , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH RFC 8/8] clk: sunxi-ng: a733: Add reset lines Date: Thu, 2 Jul 2026 14:11:40 -0400 Message-ID: <20260702181140.883070-1-enzo.adriano.code@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260310-a733-clk-v1-8-36b4e9b24457@pigmoral.tech> References: <20260310-a733-clk-v1-8-36b4e9b24457@pigmoral.tech> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260702_111146_253778_CFA771C2 X-CRM114-Status: UNSURE ( 6.80 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Hi Junhui, Same exercise for the reset map: I compared all 121 entries' offsets and bit positions against the public A733 User Manual V0.92. 115 match the manual exactly (including the multi-bit GMAC0 entry - 0x141C bits 16/17 per section 4.1.6.212 - and RST_BUS_SYSDAP at 0x7ac, which is what makes the gate offset in patch 7/8 stand out). The six that have no register in the public manual, in case you want to add provenance notes near them (as already discussed for other undocumented IDs in this series): - RST_BUS_SPI4 { 0x0F2C, BIT(16) } - RST_BUS_SGPIO { 0x1064, BIT(16) } - RST_BUS_LPC { 0x1084, BIT(16) } - RST_BUS_GMAC1 { 0x142C, BIT(16) } [GMAC1 question] - RST_BUS_GMAC1_AXI { 0x142C, BIT(17) } [GMAC1 question] - RST_BUS_TCON_LCD2 { 0x1514, BIT(16) } - the manual documents only VO0_TCONLCD0_BGR (0x1504) and VO0_TCONLCD1_BGR (0x150C); there is no TCONLCD2 register set in V0.92 Everything else in the reset map checks out against the manual. This analysis was done with AI assistance (Claude Code, claude-fable-5) and each finding was checked against the cited sources. Thanks, Enzo _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv