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Wed, 12 Aug 2026 05:21:47 -0700 (PDT) Received: from hsinchu16.internal.sifive.com ([210.176.154.34]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4997aaa5d04sm65858905e9.2.2026.08.12.05.21.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Aug 2026 05:21:45 -0700 (PDT) From: Yu-Chien Peter Lin To: devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, samuel.holland@sifive.com, dlan@kernel.org, dfustini@oss.tenstorrent.com, michal.simek@amd.com, junhui.liu@pigmoral.tech, darshan.prajapati@einfochips.com, akpm@linux-foundation.org, zhangchunyan@iscas.ac.cn, luxu.kernel@bytedance.com, pincheng.plct@isrc.iscas.ac.cn, nick.hu@sifive.com, jim.shu@sifive.com, zong.li@sifive.com, greentime.hu@sifive.com, robin.randhawa@sifive.com, scott@riscstar.com, dave.patel@riscstar.com, raymond.mao@riscstar.com, anup@brainfault.org, pawandeep.oza@oss.qualcomm.com, Yu-Chien Peter Lin Subject: [RFC PATCH v3 0/3] dt-bindings: riscv: Add RISC-V Worlds and SiFive WorldGuard DT bindings Date: Wed, 12 Aug 2026 20:21:28 +0800 Message-ID: <20260812122131.1534906-1-peter.lin@sifive.com> X-Mailer: git-send-email 2.48.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260812_052149_986899_592E869F X-CRM114-Status: UNSURE ( 8.50 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org This series introduces device tree bindings for the RISC-V Worlds ISA extensions and the SiFive WorldGuard Checker hardware. RISC-V Worlds is a set of standard ISA extensions (Smwid, Smlwid, Smlwidlist, Smwiddeleg, Sswid) that enable hardware-enforced context isolation by tagging each system transaction with a World ID (WID). The extensions allow platform firmware to assign WIDs to privilege levels, execution contexts, or isolation domains, and delegatable WID management across privilege boundaries. The SiFive WorldGuard Checker (wgChecker) is a hardware firewall positioned in the system interconnect fabric. It inspects the WID of every transaction and enforces access control policies on memory regions and memory-mapped I/O devices. The wgChecker is based on the access-controllers framework, allowing protected devices to declare their access requirements via standard phandle references. This is submitted as [RFC] because the RISC-V Worlds specification is not yet ratified. The extension descriptions in extensions.yaml carry placeholder "TBD" commit references; these will be updated to the actual ratification commit before the series is merged. Yu-Chien Peter Lin (3): dt-bindings: riscv: Add Worlds ISA extensions dt-bindings: riscv: Add Worlds per-hart properties dt-bindings: access-controllers: Add SiFive WorldGuard Checker .../access-controllers/sifive,wgchecker2.yaml | 178 ++++++++++++++++++ .../devicetree/bindings/riscv/cpus.yaml | 44 +++++ .../devicetree/bindings/riscv/extensions.yaml | 53 ++++++ 3 files changed, 275 insertions(+) create mode 100644 Documentation/devicetree/bindings/access-controllers/sifive,wgchecker2.yaml -- 2.43.7 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv