From: Conor Dooley <conor@kernel.org>
To: Mayuresh Chitale <mayuresh.chitale@oss.qualcomm.com>
Cc: Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Paul Walmsley <pjw@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alex@ghiti.fr>,
Guodong Xu <docular.xu@gmail.com>,
Andrew Morton <akpm@linux-foundation.org>,
Deepak Gupta <debug@rivosinc.com>,
Xu Lu <luxu.kernel@bytedance.com>,
Pincheng Wang <pincheng.plct@isrc.iscas.ac.cn>,
devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [RFC PATCH 1/3] dt-bindings: riscv: Add Sspesa and Ssplcofi extensions
Date: Tue, 18 Aug 2026 10:35:51 +0100 [thread overview]
Message-ID: <20260818-hunger-module-a44d9716010d@spud> (raw)
In-Reply-To: <20260817160222.3313295-2-mayuresh.chitale@oss.qualcomm.com>
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On Mon, Aug 17, 2026 at 09:32:17PM +0530, Mayuresh Chitale wrote:
> Document the RISC-V Performance Event Sampling extensions Sspesa
> (Precise Event Sample Attribution) and Ssplcofi (Precise Local Counter
> Overflow Interrupt) in the ISA extensions binding.
>
> Add a dependency rule requiring Sspesa to be present whenever Ssplcofi
> is present.
>
> Signed-off-by: Mayuresh Chitale <mayuresh.chitale@oss.qualcomm.com>
Why is this series RFC?
Cheers,
Conor.
> ---
> .../devicetree/bindings/riscv/extensions.yaml | 19 +++++++++++++++++++
> 1 file changed, 19 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
> index 5ffc40d599c0..f316b93754ff 100644
> --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
> +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
> @@ -232,6 +232,18 @@ properties:
> ratified at commit d70011dde6c2 ("Update to ratified state")
> of riscv-j-extension.
>
> + - const: sspesa
> + description: |
> + The standard Sspesa supervisor-level extension for precise event
> + sample attribution, as defined in the RISC-V Performance Event
> + Sampling specification.
> +
> + - const: ssplcofi
> + description: |
> + The standard Ssplcofi supervisor-level extension for precise local
> + counter overflow interrupts, as defined in the RISC-V Performance
> + Event Sampling specification. Ssplcofi depends on Sspesa.
> +
> - const: ssstateen
> description: |
> The standard Ssstateen extension for supervisor-mode view of the
> @@ -934,6 +946,13 @@ properties:
> const: smnpm
> - contains:
> const: ssnpm
> + # Ssplcofi depends on Sspesa
> + - if:
> + contains:
> + const: ssplcofi
> + then:
> + contains:
> + const: sspesa
> # Za64rs and Ziccrse depend on Zalrsc or A
> - if:
> contains:
> --
> 2.43.0
>
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next prev parent reply other threads:[~2026-08-18 9:36 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-17 16:02 [RFC PATCH 0/3] RISC-V Sspesa: Linux perf precise sample attribution Mayuresh Chitale
2026-08-17 16:02 ` [RFC PATCH 1/3] dt-bindings: riscv: Add Sspesa and Ssplcofi extensions Mayuresh Chitale
2026-08-18 9:35 ` Conor Dooley [this message]
2026-08-17 16:02 ` [RFC PATCH 2/3] riscv: Add detection for " Mayuresh Chitale
2026-08-17 16:02 ` [RFC PATCH 3/3] perf/riscv: Use Sspesa for precise sample attribution Mayuresh Chitale
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