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From: Jason Gunthorpe <jgg@nvidia.com>
To: Andrew Jones <andrew.jones@oss.qualcomm.com>
Cc: linux-riscv@lists.infradead.org, iommu@lists.linux.dev,
	linux-kernel@vger.kernel.org, tomasz.jeznach@linux.dev,
	tjeznach@rivosinc.com, joro@8bytes.org, will@kernel.org,
	robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com,
	anup@brainfault.org, tglx@kernel.org, kevin.tian@intel.com,
	fangyu.yu@linux.alibaba.com
Subject: Re: [PATCH v4 02/21] iommufd: Add iommufd_sw_map_msi()
Date: Fri, 21 Aug 2026 09:02:04 -0300	[thread overview]
Message-ID: <20260821120204.GF244917@nvidia.com> (raw)
In-Reply-To: <gr2h3ktgacozyo7rdggkxsg5mbdtzcnimaawd24c37hnf2tun3@hqivsenaq5wd>

On Fri, Aug 21, 2026 at 01:07:03PM +0200, Andrew Jones wrote:

> > What I rather expected was for riscv to have a PA window that is very
> > big and not just one page, eg adjust iommu_dma_prepare_msi() so you
> > can pass in the entire PA space that you need for the affinity
> > changes. Maybe this is a list of phys_addr_t ?
> 
> That's more or less what this series does. 

But it does it in a completely different way, and I'm struggling to
see any justification for this.

Again, just pass your list of PAs to iommu_dma_prepare_msi() from the
irq domain seems like the easiest and most ARM aligned thing.

When you need a new IOVA for an affinity change the PA's are already
mapped a simple offset calculation is that is needed.

No weridness in domain allocation, no messing with irq stuff in a
finalize function, no hackery to iommufd.

> There's no big PA window
> because the IMSIC PAs aren't generally contiguous. iommu_dma_map_msi()
> factors the mapping operation out of iommu_dma_prepare_msi() and returns
> each IOVA directly. A batched list API would be possible, but it would
> only move the loop.

But it keeps the entire flow consistent. Trying to pre-map MSIs and
mangle all sorts of things in the riscv driver is undoing the
generalization and what is expected to be be common code.

I don't want to see any mapping of msi in the rsicv iommu driver at
all, that should be the most important design point.

Jason

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  reply	other threads:[~2026-08-21 12:02 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-08-20 21:41 [PATCH v4 00/21] iommu/riscv: Enable MSI remapping, IOMMU_DMA and VFIO Andrew Jones
2026-08-20 21:41 ` [PATCH v4 01/21] iommufd: Convert struct iommufd_sw_msi_maps to a growable bitmap Andrew Jones
2026-08-20 21:41 ` [PATCH v4 02/21] iommufd: Add iommufd_sw_map_msi() Andrew Jones
2026-08-20 22:09   ` Jason Gunthorpe
2026-08-21 11:07     ` Andrew Jones
2026-08-21 12:02       ` Jason Gunthorpe [this message]
2026-08-21 13:47         ` Andrew Jones
2026-08-21 14:00           ` Jason Gunthorpe
2026-08-21 14:23             ` Andrew Jones
2026-08-21 14:31               ` Jason Gunthorpe
2026-08-20 21:41 ` [PATCH v4 03/21] iommu/dma: Add iommu_dma_sw_map_msi() Andrew Jones
2026-08-20 21:41 ` [PATCH v4 04/21] iommu/dma: Add iommu_dma_map_msi() Andrew Jones
2026-08-20 21:41 ` [PATCH v4 05/21] iommu: Document MSI mapping during domain replacement Andrew Jones
2026-08-20 21:41 ` [PATCH v4 06/21] genirq/msi: Provide DOMAIN_BUS_MSI_REMAP Andrew Jones
2026-08-20 21:41 ` [PATCH v4 07/21] irqchip/riscv-imsic: Compose MSI updates through the hierarchy Andrew Jones
2026-08-20 21:41 ` [PATCH v4 08/21] iommu/riscv: Add IRQ domain for interrupt remapping Andrew Jones
2026-08-20 21:41 ` [PATCH v4 09/21] iommu/riscv: Refresh platform MSI domain before IR setup Andrew Jones
2026-08-20 21:41 ` [PATCH v4 10/21] iommu/riscv: Prepare info->domain for concurrent RCU read access Andrew Jones
2026-08-20 21:41 ` [PATCH v4 11/21] iommu/riscv: Reserve an MSI IOVA window for iommufd Andrew Jones
2026-08-20 21:41 ` [PATCH v4 12/21] iommu/riscv: Pre-map IMSIC MSI targets Andrew Jones
2026-08-20 21:41 ` [PATCH v4 13/21] iommu/riscv: Preserve MSI IOVA state across domain replacement Andrew Jones
2026-08-20 21:52   ` Jason Gunthorpe
2026-08-21 11:14     ` Andrew Jones
2026-08-21 13:22       ` Jason Gunthorpe
2026-08-21 13:56         ` Andrew Jones
2026-08-20 21:41 ` [PATCH v4 14/21] iommu/riscv: Gate direct identity boundary switches with live MSIs Andrew Jones
2026-08-20 21:41 ` [PATCH v4 15/21] iommu/riscv: Remap IMSIC targets during MSI composition Andrew Jones
2026-08-20 21:41 ` [PATCH v4 16/21] iommu/dma: Enable IOMMU_DMA for 64-bit RISC-V Andrew Jones
2026-08-20 21:41 ` [PATCH v4 17/21] iommu/riscv: Report cache coherency capability Andrew Jones
2026-08-20 21:47   ` Jason Gunthorpe
2026-08-21 11:15     ` Andrew Jones
2026-08-20 21:41 ` [PATCH v4 18/21] vfio: enable IOMMU_TYPE1 for RISC-V Andrew Jones
2026-08-20 21:41 ` [PATCH v4 19/21] RISC-V: KVM: Enable KVM_VFIO interfaces on RISC-V arch Andrew Jones
2026-08-20 21:41 ` [PATCH v4 20/21] riscv: defconfig: Enable IOMMUFD and VFIO Andrew Jones
2026-08-20 21:41 ` [PATCH v4 21/21] selftests/vfio: Allow building on RISC-V Andrew Jones

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