From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 293A3C5DF8E for ; Fri, 21 Aug 2026 13:28:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=rf0v/rGdZ3hAL1YSBwiPGFbEznvteSfWPE0Sa91RRQk=; b=pVMooeuaYE8RY7 kk/w+eXEq/Z6BKnP9f2CCty0kyMjF3vSO14xhXGTCL6ejAytj1uCwR/v2fOP6xgwf7kg3XpgJ/bBw IHVFMCXqXNOUm5iiPs8tdC2OBPctQOCcehLhwQu5AsPw0M3RViTfU4PHNrROKYircV5X+FsigO8OE b+16CLpg2ETuSZpHfppk1WnIrp5vMJcquhVY+vJwemdHUfl4dUYd+lWfSB64Kmv7XfgliFKjVg3A8 ejsNNL7grKciGS5WocsKtxkXH52hXYy6/NyRGZWswY0MI4cedIIQaNoKKGj+aLLNkoGqvxwp0OCO5 vvJNWkJtCxSq7rLsKVEg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.99.1 #2 (Red Hat Linux)) id 1wxPI5-0000000DPCU-2ztW; Fri, 21 Aug 2026 13:28:13 +0000 Received: from out30-119.freemail.mail.aliyun.com ([115.124.30.119]) by bombadil.infradead.org with esmtps (Exim 4.99.1 #2 (Red Hat Linux)) id 1wxPI0-0000000DP6u-24FY for linux-riscv@lists.infradead.org; Fri, 21 Aug 2026 13:28:11 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1787318885; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=iJuM/I3QzzZ29IqRau9ZBf+7q6zMX3YoOle6ur78Bj0=; b=sahXKe8ruvfvO5RJ1DPTMKNif72vBPx4Eu12iAQxPUydH4a8sVJ9g+0U8tJvFz4vpdxN/F8BnxgDcvsItgdbv4XgGuVSvUb5fbpbzMCxHhq17bbWFSREAABpdch0y2gtZQuHDflL5xQ7NspqjAwTvhncdzns47pasETW7oqbPzM= X-Alimail-AntiSpam: AC=PASS;BC=-1|-1;BR=01201311R131e4;CH=green;DM=||false|;DS=||;FP=0|-1|-1|-1|0|-1|-1|-1;HT=maildocker-contentspam033037033178;MF=fangyu.yu@linux.alibaba.com;NM=1;PH=DS;RN=24;SR=0;TI=SMTPD_---0X9MSFH4_1787318882; Received: from localhost.localdomain(mailfrom:fangyu.yu@linux.alibaba.com fp:SMTPD_---0X9MSFH4_1787318882 cluster:ay36) by smtp.aliyun-inc.com; Fri, 21 Aug 2026 21:28:04 +0800 From: fangyu.yu@linux.alibaba.com To: tomasz.jeznach@linux.dev, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, baolu.lu@linux.intel.com, jroedel@suse.de, zong.li@sifive.com, andrew.jones@oss.qualcomm.com, anup@brainfault.org, jgg@nvidia.com, jgg@ziepe.ca, kevin.tian@intel.com, atish.patra@linux.dev, skhawaja@google.com, vasant.hegde@amd.com Cc: fangyu.yu@linux.alibaba.com, guoren@kernel.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [RFC PATCH v3 05/10] iommu/riscv: support GSCID and GVMA invalidation command Date: Fri, 21 Aug 2026 21:27:45 +0800 Message-Id: <20260821132749.82070-6-fangyu.yu@linux.alibaba.com> X-Mailer: git-send-email 2.39.3 (Apple Git-146) In-Reply-To: <20260821132749.82070-1-fangyu.yu@linux.alibaba.com> References: <20260821132749.82070-1-fangyu.yu@linux.alibaba.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260821_062809_109029_7D4B2006 X-CRM114-Status: GOOD ( 14.35 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Zong Li This patch adds a ID Allocator for GSCID and a wrap for setting up GSCID in IOTLB invalidation command. Set up iohgatp to enable second stage table and flush stage-2 table if the GSCID is set. The GSCID of domain should be freed when release domain. GSCID will be allocated for parent domain in nested IOMMU process. Signed-off-by: Zong Li Signed-off-by: Fangyu Yu --- drivers/iommu/riscv/iommu-bits.h | 7 ++++ drivers/iommu/riscv/iommu.c | 62 ++++++++++++++++++++++++++------ 2 files changed, 58 insertions(+), 11 deletions(-) diff --git a/drivers/iommu/riscv/iommu-bits.h b/drivers/iommu/riscv/iommu-bits.h index f2ef9bd3cde9..65d1f2250011 100644 --- a/drivers/iommu/riscv/iommu-bits.h +++ b/drivers/iommu/riscv/iommu-bits.h @@ -720,6 +720,13 @@ static inline void riscv_iommu_cmd_inval_vma(struct riscv_iommu_command *cmd) cmd->dword1 = 0; } +static inline void riscv_iommu_cmd_inval_gvma(struct riscv_iommu_command *cmd) +{ + cmd->dword0 = FIELD_PREP(RISCV_IOMMU_CMD0_OPCODE, RISCV_IOMMU_CMD_IOTINVAL_OPCODE) | + FIELD_PREP(RISCV_IOMMU_CMD0_FUNC, RISCV_IOMMU_CMD_IOTINVAL_FUNC_GVMA); + cmd->dword1 = 0; +} + static inline void riscv_iommu_cmd_inval_set_addr(struct riscv_iommu_command *cmd, u64 addr) { diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c index c5b6214ee672..99f05f1db35b 100644 --- a/drivers/iommu/riscv/iommu.c +++ b/drivers/iommu/riscv/iommu.c @@ -48,6 +48,10 @@ static DEFINE_IDA(riscv_iommu_pscids); #define RISCV_IOMMU_MAX_PSCID (BIT(20) - 1) +/* IOMMU GSCID allocation namespace. */ +static DEFINE_IDA(riscv_iommu_gscids); +#define RISCV_IOMMU_MAX_GSCID (BIT(16) - 1) + /* Device resource-managed allocations */ struct riscv_iommu_devres { void *addr; @@ -819,6 +823,7 @@ struct riscv_iommu_domain { struct list_head bonds; spinlock_t lock; /* protect bonds list updates. */ int pscid; + int gscid; }; PT_IOMMU_CHECK_DOMAIN(struct riscv_iommu_domain, riscvpt.iommu, domain); @@ -981,7 +986,7 @@ static void riscv_iommu_tlbi_calc(struct riscv_iommu_tlbi *tlbi, } static void riscv_iommu_iotlb_inval_iommu(struct riscv_iommu_device *iommu, - int pscid, + int pscid, int gscid, struct riscv_iommu_tlbi *tlbi) { bool use_nl = tlbi->non_leaf && @@ -989,8 +994,13 @@ static void riscv_iommu_iotlb_inval_iommu(struct riscv_iommu_device *iommu, struct riscv_iommu_command cmd; unsigned int i; - riscv_iommu_cmd_inval_vma(&cmd); - riscv_iommu_cmd_inval_set_pscid(&cmd, pscid); + if (gscid) { + riscv_iommu_cmd_inval_gvma(&cmd); + riscv_iommu_cmd_inval_set_gscid(&cmd, gscid); + } else { + riscv_iommu_cmd_inval_vma(&cmd); + riscv_iommu_cmd_inval_set_pscid(&cmd, pscid); + } /* * If non-leaf entries were changed and the IOMMU doesn't @@ -1074,7 +1084,7 @@ static void riscv_iommu_iotlb_inval(struct riscv_iommu_domain *domain, if (iommu == prev) continue; - riscv_iommu_iotlb_inval_iommu(iommu, domain->pscid, &tlbi); + riscv_iommu_iotlb_inval_iommu(iommu, domain->pscid, domain->gscid, &tlbi); prev = iommu; } @@ -1208,6 +1218,7 @@ static void riscv_iommu_iodir_update(struct riscv_iommu_device *iommu, WRITE_ONCE(dc->fsc, new_dc->fsc); WRITE_ONCE(dc->ta, new_dc->ta & RISCV_IOMMU_PC_TA_PSCID); + WRITE_ONCE(dc->iohgatp, new_dc->iohgatp); /* Update device context, write TC.V as the last step. */ dma_wmb(); WRITE_ONCE(dc->tc, tc); @@ -1258,16 +1269,19 @@ static void riscv_iommu_free_paging_domain(struct iommu_domain *iommu_domain) WARN_ON(!list_empty(&domain->bonds)); - if ((int)domain->pscid > 0) + if (domain->pscid > 0) ida_free(&riscv_iommu_pscids, domain->pscid); + if (domain->gscid > 0) + ida_free(&riscv_iommu_gscids, domain->gscid); pt_iommu_deinit(&domain->riscvpt.iommu); kfree(domain); } -static bool riscv_iommu_pt_supported(struct riscv_iommu_device *iommu, int pgd_mode) +static bool riscv_iommu_fsc_supported(struct riscv_iommu_device *iommu, + int mode) { - switch (pgd_mode) { + switch (mode) { case RISCV_IOMMU_DC_FSC_IOSATP_MODE_SV39: return iommu->caps & RISCV_IOMMU_CAPABILITIES_SV39; @@ -1280,6 +1294,22 @@ static bool riscv_iommu_pt_supported(struct riscv_iommu_device *iommu, int pgd_m return false; } +static bool riscv_iommu_iohgatp_supported(struct riscv_iommu_device *iommu, + int mode) +{ + switch (mode) { + case RISCV_IOMMU_DC_IOHGATP_MODE_SV39X4: + return iommu->caps & RISCV_IOMMU_CAPABILITIES_SV39X4; + + case RISCV_IOMMU_DC_IOHGATP_MODE_SV48X4: + return iommu->caps & RISCV_IOMMU_CAPABILITIES_SV48X4; + + case RISCV_IOMMU_DC_IOHGATP_MODE_SV57X4: + return iommu->caps & RISCV_IOMMU_CAPABILITIES_SV57X4; + } + return false; +} + static int riscv_iommu_attach_paging_domain(struct iommu_domain *iommu_domain, struct device *dev, struct iommu_domain *old) @@ -1292,11 +1322,21 @@ static int riscv_iommu_attach_paging_domain(struct iommu_domain *iommu_domain, pt_iommu_riscv_64_hw_info(&domain->riscvpt, &pt_info); - if (!riscv_iommu_pt_supported(iommu, pt_info.fsc_iosatp_mode)) - return -ENODEV; + if (domain->gscid) { + if (!riscv_iommu_iohgatp_supported(iommu, pt_info.iohgatp_mode)) + return -ENODEV; + + dc.iohgatp = + FIELD_PREP(RISCV_IOMMU_DC_IOHGATP_MODE, pt_info.iohgatp_mode) | + FIELD_PREP(RISCV_IOMMU_DC_IOHGATP_GSCID, domain->gscid) | + FIELD_PREP(RISCV_IOMMU_DC_IOHGATP_PPN, pt_info.ppn); + } else { + if (!riscv_iommu_fsc_supported(iommu, pt_info.fsc_iosatp_mode)) + return -ENODEV; - dc.fsc = FIELD_PREP(RISCV_IOMMU_PC_FSC_MODE, pt_info.fsc_iosatp_mode) | - FIELD_PREP(RISCV_IOMMU_PC_FSC_PPN, pt_info.ppn); + dc.fsc = FIELD_PREP(RISCV_IOMMU_PC_FSC_MODE, pt_info.fsc_iosatp_mode) | + FIELD_PREP(RISCV_IOMMU_PC_FSC_PPN, pt_info.ppn); + } dc.ta = FIELD_PREP(RISCV_IOMMU_PC_TA_PSCID, domain->pscid) | RISCV_IOMMU_PC_TA_V; -- 2.50.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv