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Mon, 31 Aug 2026 11:35:35 +0000 Received: from ZQ4PR01MB1202.CHNPR01.prod.partner.outlook.cn ([fe80::e7d4:256c:b066:850d]) by ZQ4PR01MB1202.CHNPR01.prod.partner.outlook.cn ([fe80::e7d4:256c:b066:850d%4]) with mapi id 15.21.0315.011; Mon, 31 Aug 2026 11:35:35 +0000 From: Changhuang Liang To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Emil Renner Berthing , Paul Walmsley , Albert Ou , Palmer Dabbelt , Alexandre Ghiti , Philipp Zabel , Bartosz Golaszewski Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Lianfeng Ouyang , Changhuang Liang Subject: [PATCH v7 09/21] dt-bindings: pinctrl: Add starfive,jhb100-sys2-pinctrl Date: Mon, 31 Aug 2026 04:35:02 -0700 Message-Id: <20260831113514.66382-10-changhuang.liang@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260831113514.66382-1-changhuang.liang@starfivetech.com> References: <20260831113514.66382-1-changhuang.liang@starfivetech.com> X-ClientProxiedBy: ZQ0PR01CA0013.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:5::8) To ZQ4PR01MB1202.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:17::6) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: ZQ4PR01MB1202:EE_|ZQ4PR01MB1332:EE_ X-MS-Office365-Filtering-Correlation-Id: 82dcffa6-1465-4d65-7124-08df0753f94d X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|52116014|366016|1800799024|376014|7416014|18002099003|38350700014|22082099003|56012099006|3023799007|921020|10067099003|6133799003; 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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Add pinctrl bindings for StarFive JHB100 SoC System-2(sys2) pinctrl controller. Signed-off-by: Changhuang Liang --- .../pinctrl/starfive,jhb100-sys2-pinctrl.yaml | 165 ++++++++++++++++++ .../pinctrl/starfive,jhb100-pinctrl.h | 39 +++++ 2 files changed, 204 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jhb100-sys2-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-sys2-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-sys2-pinctrl.yaml new file mode 100644 index 000000000000..e2d18e0d4916 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-sys2-pinctrl.yaml @@ -0,0 +1,165 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/starfive,jhb100-sys2-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JHB100 System-2 Pin Controller + +description: | + Pinctrl bindings for JHB100 RISC-V SoC from StarFive Technology Ltd. + + The JHB100 SoC has 13 pinctrl domains - sys0, sys0h, sys1, sys2, per0, per1, + per2, per2pok, per3, adc0, adc1, emmc, and vga. + This document provides an overview of the "sys2" pinctrl domain. + + The "sys2" domain has a pin controller which provides + - function selection for GPIO pads. + - GPIO pad configuration. + - GPIO interrupt handling. + + In the SYS2 Pin Controller, there are 37 multi-function GPIO_PADs. Each of + them can be multiplexed to different hardware blocks through function + selection. Each iopad has a maximum of up to 4 functions - 0, 1, 2, and 3. + Function 0 is the default function which is the GPIO function. + Function 1, 2, and 3 are the alternate functions or peripheral signals that + can be routed to the iopad. The function selection can be carried out by + writing the function number to the iopad function select register. + + Each iopad is configurable with parameters such as input-enable, internal + pull-up/pull-down bias, drive strength, schmitt trigger, slew rate, input + debounce nanoseconds, power source. + +maintainers: + - Changhuang Liang + +properties: + compatible: + items: + - const: starfive,jhb100-sys2-pinctrl + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + gpio-controller: true + + '#gpio-cells': + const: 2 + + gpio-ranges: true + + gpio-line-names: true + +patternProperties: + '-grp$': + type: object + additionalProperties: false + patternProperties: + '-pins$': + type: object + description: | + A pinctrl node should contain at least one subnode representing the + pinctrl groups available in the domain. Each subnode will list the + pins it needs, and how they should be configured, with regard to + function selection, bias, input enable/disable, input schmitt + trigger enable/disable, slew-rate, input debounce nanoseconds, + power-source and drive-strength. + allOf: + - $ref: /schemas/pinctrl/pincfg-node.yaml + - $ref: /schemas/pinctrl/pinmux-node.yaml + additionalProperties: false + + properties: + pins: + description: + The list of IOs that properties in the pincfg node apply to. + + function: + description: + A string containing the name of the function to mux for these + pins. + enum: [ gpio, host0_port80, host1_port80, jtag, smbalert, uart ] + + bias-disable: true + + bias-pull-down: + type: boolean + + bias-pull-up: + type: boolean + + drive-strength: + enum: [ 2, 4, 8, 12 ] + + drive-strength-microamp: + enum: [ 2000, 4000, 8000, 12000 ] + + input-debounce-ns: + minimum: 0 + maximum: 10485680 + description: + Debounce time in nanoseconds. The hardware counts in 80 ns + stages with a 17-bit counter, so the maximum is 10485680 ns. + + input-disable: true + + input-enable: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + power-source: + enum: [ 1800, 3300 ] + description: I/O voltage in millivolt. + + slew-rate: + enum: [ 0, 1 ] + default: 0 + description: | + 0: slow + 1: fast + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - '#interrupt-cells' + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + pinctrl_sys2: pinctrl@13082000 { + compatible = "starfive,jhb100-sys2-pinctrl"; + reg = <0x0 0x13082000 0x0 0x1000>; + interrupts = <59>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_sys2 0 0 37>; + }; + }; diff --git a/include/dt-bindings/pinctrl/starfive,jhb100-pinctrl.h b/include/dt-bindings/pinctrl/starfive,jhb100-pinctrl.h index 30704a5a3418..e701c30913ce 100644 --- a/include/dt-bindings/pinctrl/starfive,jhb100-pinctrl.h +++ b/include/dt-bindings/pinctrl/starfive,jhb100-pinctrl.h @@ -38,4 +38,43 @@ #define PADNUM_SYS1_GPIO_A22 6 #define PADNUM_SYS1_GPIO_A23 7 +/* sys2 pad numbers */ +#define PADNUM_SYS2_GPIO_A24 0 +#define PADNUM_SYS2_GPIO_A25 1 +#define PADNUM_SYS2_GPIO_A26 2 +#define PADNUM_SYS2_GPIO_A27 3 +#define PADNUM_SYS2_GPIO_A28 4 +#define PADNUM_SYS2_GPIO_A29 5 +#define PADNUM_SYS2_GPIO_A30 6 +#define PADNUM_SYS2_GPIO_A31 7 +#define PADNUM_SYS2_GPIO_A32 8 +#define PADNUM_SYS2_GPIO_A33 9 +#define PADNUM_SYS2_GPIO_A34 10 +#define PADNUM_SYS2_GPIO_A35 11 +#define PADNUM_SYS2_GPIO_A36 12 +#define PADNUM_SYS2_GPIO_A37 13 +#define PADNUM_SYS2_GPIO_A38 14 +#define PADNUM_SYS2_GPIO_A39 15 +#define PADNUM_SYS2_GPIO_A40 16 +#define PADNUM_SYS2_GPIO_A41 17 +#define PADNUM_SYS2_GPIO_A42 18 +#define PADNUM_SYS2_GPIO_A43 19 +#define PADNUM_SYS2_GPIO_A44 20 +#define PADNUM_SYS2_GPIO_A45 21 +#define PADNUM_SYS2_GPIO_A46 22 +#define PADNUM_SYS2_GPIO_A47 23 +#define PADNUM_SYS2_GPIO_A48 24 +#define PADNUM_SYS2_GPIO_A49 25 +#define PADNUM_SYS2_GPIO_A50 26 +#define PADNUM_SYS2_GPIO_A51 27 +#define PADNUM_SYS2_GPIO_A52 28 +#define PADNUM_SYS2_GPIO_A53 29 +#define PADNUM_SYS2_GPIO_A54 30 +#define PADNUM_SYS2_GPIO_A55 31 +#define PADNUM_SYS2_GPIO_A56 32 +#define PADNUM_SYS2_GPIO_A57 33 +#define PADNUM_SYS2_GPIO_A58 34 +#define PADNUM_SYS2_GPIO_A59 35 +#define PADNUM_SYS2_GPIO_A60 36 + #endif -- 2.25.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv