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[86.49.251.7]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49cd2e9d9fcsm219790525e9.1.2026.08.31.08.00.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Aug 2026 08:00:00 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org, iommu@lists.linux.dev Cc: linux-kernel@vger.kernel.org, tomasz.jeznach@linux.dev, tjeznach@rivosinc.com, jgg@ziepe.ca, jgg@nvidia.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, anup@brainfault.org, tglx@kernel.org, kevin.tian@intel.com, fangyu.yu@linux.alibaba.com Subject: [PATCH v5 10/17] iommu/riscv: Reserve an MSI IOVA window for iommufd Date: Mon, 31 Aug 2026 16:59:36 +0200 Message-ID: <20260831145943.313726-11-andrew.jones@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260831145943.313726-1-andrew.jones@oss.qualcomm.com> References: <20260831145943.313726-1-andrew.jones@oss.qualcomm.com> MIME-Version: 1.0 X-Proofpoint-Spam-Info: AW1haW4tMjYwODMxMDEyOSBTYWx0ZWRfX19YpBK9MNSYy 2m8Dxh5HPfNpK0RgBkDq5xiEQ4laP55dSDKAUWlKy4WAMRYk5n+kMjxPxxc9dXxjoJwL6y23obw bxyjx1jdPqOqD4YITz8OeNz0NQLbK+w= X-Authority-Analysis: v=2.4 cv=CpaPtH4D c=1 sm=1 tr=0 ts=6a9596f3 cx=c_pps a=50t2pK5VMbmlHzFWWp8p/g==:117 a=on9AXyaqQ0RhfYpiXjjEXA==:17 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=EUspDBNiAAAA:8 a=BnA8ekc9z0NdPsKvynsA:9 a=IoWCM6iH3mJn3m4BftBB:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODMxMDEyOSBTYWx0ZWRfXxGyzogdwRtjA j2zjUjOqUMmKJMOEG7Qn3u76dIO0iV+CgPbRV5wp6++qFGh2ZIAHbZlUtUm7KV9bk06xEznWEQE TnXxpwkXQT8RUzXSwLa90AiUcS055kjqtWP+UOPKpMxgAQNdkYl699saF+j1fE9YZP5mDnz3AGz bQbjEugx5pyy9R5qOrsX9UvAB7L6ATwDKyc/7bfQwCR6b/GW1cl8fBqlgVNZUedCsHKBB1Pn9Dr u5HOnxkDWCWXtPMQLLxb0gs8LbU3w7ZYq6CIoPx1y3fO/n4Ya6ZETX5WhogAdMhGT1RGAtxDaQx yJmvRuVR5jWyYfLiNPBj3hTHoUlki2D+yH7ykiNieNnWGm5jX7e6nRd/+GlkZiRX1esX/xQMpbZ +P4g2TUd7QS4VIlMn35ThoQNMsFkOanu/rWQ6NSgBeuErrHmIl7fGNEZ1xwqJuuHLNS/bc5IkZi B4Z4TYEn4snJ9Snxphw== X-Proofpoint-ORIG-GUID: aZ_mC72NFdnPz8OtKfB1lOIJsn7D8UHD X-Proofpoint-GUID: aZ_mC72NFdnPz8OtKfB1lOIJsn7D8UHD X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-31_05,2026-08-27_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 adultscore=0 lowpriorityscore=0 clxscore=1015 priorityscore=1501 malwarescore=0 phishscore=0 suspectscore=0 spamscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608310129 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260831_080004_749643_9FC5FA87 X-CRM114-Status: GOOD ( 18.51 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org iommufd requires an IOMMU_RESV_SW_MSI region to allocate stable IOVAs for MSI targets. Advertise such a region when the device uses an IMSIC MSI hierarchy so interrupt remapping can map IMSIC pages instead of falling back to physical addresses. Reserve one page per possible CPU, sufficient for each supervisor IMSIC page. Place the window at 128 MiB, matching the established ARM SMMU MSI IOVA convention rather than introducing an architecture-specific choice. Signed-off-by: Andrew Jones --- drivers/iommu/riscv/iommu.c | 20 ++++++++++++++++++++ drivers/iommu/riscv/iommu.h | 4 ++++ drivers/irqchip/irq-riscv-imsic-state.c | 22 ++++++++++++++++++++++ include/linux/irqchip/riscv-imsic.h | 6 ++++++ 4 files changed, 52 insertions(+) diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c index e5818ce44515..7c4a250d61ca 100644 --- a/drivers/iommu/riscv/iommu.c +++ b/drivers/iommu/riscv/iommu.c @@ -20,10 +20,12 @@ #include #include #include +#include #include #include #include +#include "../dma-iommu.h" #include "../iommu-pages.h" #include "iommu-bits.h" #include "iommu.h" @@ -1492,6 +1494,23 @@ static void riscv_iommu_release_device(struct device *dev) kfree_rcu_mightsleep(info); } +static void riscv_iommu_get_resv_regions(struct device *dev, struct list_head *head) +{ + struct iommu_resv_region *region; + + if (imsic_dev_has_imsic_msi_parent(dev)) { + /* Each hart has one S-mode IMSIC page, a.k.a MSI target page */ + region = iommu_alloc_resv_region(RISCV_IOMMU_MSI_IOVA_BASE, + (size_t)num_possible_cpus() * PAGE_SIZE, + IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO, + IOMMU_RESV_SW_MSI, GFP_KERNEL); + if (region) + list_add_tail(®ion->list, head); + } + + iommu_dma_get_resv_regions(dev, head); +} + static const struct iommu_ops riscv_iommu_ops = { .of_xlate = riscv_iommu_of_xlate, .capable = riscv_iommu_capable, @@ -1502,6 +1521,7 @@ static const struct iommu_ops riscv_iommu_ops = { .device_group = riscv_iommu_device_group, .probe_device = riscv_iommu_probe_device, .release_device = riscv_iommu_release_device, + .get_resv_regions = riscv_iommu_get_resv_regions, }; static int riscv_iommu_init_check(struct riscv_iommu_device *iommu) diff --git a/drivers/iommu/riscv/iommu.h b/drivers/iommu/riscv/iommu.h index 46df79dd5495..078ed0ea65bc 100644 --- a/drivers/iommu/riscv/iommu.h +++ b/drivers/iommu/riscv/iommu.h @@ -14,9 +14,13 @@ #include #include #include +#include #include "iommu-bits.h" +/* IOVA base for the SW MSI reservation; same convention as ARM SMMU. */ +#define RISCV_IOMMU_MSI_IOVA_BASE SZ_128M + struct riscv_iommu_device; struct riscv_iommu_queue { diff --git a/drivers/irqchip/irq-riscv-imsic-state.c b/drivers/irqchip/irq-riscv-imsic-state.c index b8d1bbbf42f7..df38a7670a89 100644 --- a/drivers/irqchip/irq-riscv-imsic-state.c +++ b/drivers/irqchip/irq-riscv-imsic-state.c @@ -64,6 +64,28 @@ const struct imsic_global_config *imsic_get_global_config(void) } EXPORT_SYMBOL_GPL(imsic_get_global_config); +/** + * imsic_dev_has_imsic_msi_parent - Check for an IMSIC MSI parent + * @dev: Device to check + * + * Return: true if @dev's MSI domain or any parent domain is the IMSIC base + * domain. + */ +bool imsic_dev_has_imsic_msi_parent(struct device *dev) +{ + struct irq_domain *domain; + + if (!imsic || !imsic->base_domain) + return false; + + for (domain = dev_get_msi_domain(dev); domain; domain = domain->parent) + if (domain == imsic->base_domain) + return true; + + return false; +} +EXPORT_SYMBOL_GPL(imsic_dev_has_imsic_msi_parent); + static bool __imsic_eix_read_clear(unsigned long id, bool pend) { unsigned long isel, imask; diff --git a/include/linux/irqchip/riscv-imsic.h b/include/linux/irqchip/riscv-imsic.h index 61af3a5bea09..662cb0442424 100644 --- a/include/linux/irqchip/riscv-imsic.h +++ b/include/linux/irqchip/riscv-imsic.h @@ -81,6 +81,7 @@ struct imsic_global_config { #ifdef CONFIG_RISCV_IMSIC const struct imsic_global_config *imsic_get_global_config(void); +bool imsic_dev_has_imsic_msi_parent(struct device *dev); #else @@ -89,6 +90,11 @@ static inline const struct imsic_global_config *imsic_get_global_config(void) return NULL; } +static inline bool imsic_dev_has_imsic_msi_parent(struct device *dev) +{ + return false; +} + #endif #if IS_ENABLED(CONFIG_ACPI) && IS_ENABLED(CONFIG_RISCV_IMSIC) -- 2.43.0 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv