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[86.49.251.7]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49b90f78244sm333359565e9.10.2026.08.31.08.00.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Aug 2026 08:00:02 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org, iommu@lists.linux.dev Cc: linux-kernel@vger.kernel.org, tomasz.jeznach@linux.dev, tjeznach@rivosinc.com, jgg@ziepe.ca, jgg@nvidia.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, anup@brainfault.org, tglx@kernel.org, kevin.tian@intel.com, fangyu.yu@linux.alibaba.com Subject: [PATCH v5 11/17] irqchip/riscv-imsic: Add S-mode MSI address list Date: Mon, 31 Aug 2026 16:59:37 +0200 Message-ID: <20260831145943.313726-12-andrew.jones@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260831145943.313726-1-andrew.jones@oss.qualcomm.com> References: <20260831145943.313726-1-andrew.jones@oss.qualcomm.com> MIME-Version: 1.0 X-Proofpoint-GUID: g4kVbSahW4c6yOrK26o02zqCRGjc4tFv X-Proofpoint-Spam-Info: AW1haW4tMjYwODMxMDEyOSBTYWx0ZWRfXxNFGAWcw6O65 kd4bMhrStJokc2sdUV72AJxUQIYS1gpFG7QVVPYOMRl10UHqnCXhC5CEHRLqkgrdabIBhGdsrW4 WNFHHxLFJ5idZehhWdXomBwS7fXDYXU= X-Proofpoint-ORIG-GUID: g4kVbSahW4c6yOrK26o02zqCRGjc4tFv X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODMxMDEyOSBTYWx0ZWRfXx9VJ+hvvtKYo J2JB4xDRIFtskkGzoEmugGH+UuHfzWsvkcs89kxa7fPD2SVm9r7xHjiGjIy2R1eor8xcGmbzR+0 8YF1ZzEXk5wLY0uAdpHBPK0gtNy451gkuYkkZ7pxdoNPtNctA2o6hGxgdwfohrvBcWXMnQN55GY 8CZRu1/Rr0gfCPi1zvIPBg2L1m7JsEVSoaPZSv7VCe4Mm6qSmzWhkDA987Bh4thnQRQyewqMKa0 teYj4JmKE9amzx2Lu6gy+RJviXMXmQJogZCi5u8AKGPkdQkbjKs7V2BZkh2+D2Ien8ZupGI4YBh pdwxJD5Ug06WqWHm7q4ztYWq+mi+7mIDcRrHVpf3PYCo43tuKvykbYI2FWgKbzZPGe21wO87k77 zCZ7jHyruBGX0nrDntw1ImxQx3qNMZzptAovBem/ri/V5Wn54T3j10h1mkjPUc4u1cNGh+qsIOJ 6K5ltHDh3H2MdLTZEGg== X-Authority-Analysis: v=2.4 cv=YsY/gYYX c=1 sm=1 tr=0 ts=6a9596f4 cx=c_pps a=50t2pK5VMbmlHzFWWp8p/g==:117 a=on9AXyaqQ0RhfYpiXjjEXA==:17 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=EUspDBNiAAAA:8 a=yikt5F2n8VKCXyCzpw0A:9 a=IoWCM6iH3mJn3m4BftBB:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-31_05,2026-08-27_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 spamscore=0 clxscore=1015 suspectscore=0 phishscore=0 priorityscore=1501 adultscore=0 impostorscore=0 malwarescore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608310129 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260831_080006_358227_45560CB0 X-CRM114-Status: GOOD ( 15.29 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Upcoming RISC-V IOMMU interrupt remapping needs to map every possible host IMSIC target into one contiguous MSI IOVA range. MSI message composition then uses the target CPU's position within that range. Build an S-mode IMSIC physical address array indexed by logical CPU. Require every possible CPU to have an initialized IMSIC page before publishing the array. This preserves physical address zero as a valid target and guarantees the array has num_possible_cpus() entries. The array size and each target's index can therefore be derived directly, without storing duplicate count or per-CPU index metadata. Signed-off-by: Andrew Jones --- drivers/irqchip/irq-riscv-imsic-state.c | 32 +++++++++++++++++++++++++ drivers/irqchip/irq-riscv-imsic-state.h | 1 + 2 files changed, 33 insertions(+) diff --git a/drivers/irqchip/irq-riscv-imsic-state.c b/drivers/irqchip/irq-riscv-imsic-state.c index df38a7670a89..c7ebddd308ec 100644 --- a/drivers/irqchip/irq-riscv-imsic-state.c +++ b/drivers/irqchip/irq-riscv-imsic-state.c @@ -709,6 +709,31 @@ static int __init imsic_get_mmio_resource(struct fwnode_handle *fwnode, return of_address_to_resource(to_of_node(fwnode), index, res); } +static int __init imsic_init_smode_msi_pa(void) +{ + struct imsic_global_config *global = &imsic->global; + phys_addr_t *smode_msi_pa; + unsigned int cpu; + + smode_msi_pa = kcalloc(num_possible_cpus(), sizeof(*smode_msi_pa), GFP_KERNEL); + if (!smode_msi_pa) + return -ENOMEM; + + for_each_possible_cpu(cpu) { + struct imsic_local_config *local = per_cpu_ptr(global->local, cpu); + + if (!local->msi_va) { + kfree(smode_msi_pa); + return -ENODEV; + } + + smode_msi_pa[cpu] = local->msi_pa; + } + + imsic->smode_msi_pa = smode_msi_pa; + return 0; +} + static int __init imsic_parse_fwnode(struct fwnode_handle *fwnode, struct imsic_global_config *global, u32 *nr_parent_irqs, @@ -959,6 +984,12 @@ int __init imsic_setup_state(struct fwnode_handle *fwnode, void *opaque) goto out_local_cleanup; } + rc = imsic_init_smode_msi_pa(); + if (rc) { + pr_err("%pfwP: failed to initialize S-mode MSI addresses\n", fwnode); + goto out_local_cleanup; + } + /* Initialize matrix allocator */ rc = imsic_matrix_init(); if (rc) { @@ -984,6 +1015,7 @@ int __init imsic_setup_state(struct fwnode_handle *fwnode, void *opaque) out_free_local: free_percpu(imsic->global.local); out_free_priv: + kfree(imsic->smode_msi_pa); kfree(imsic); imsic = NULL; return rc; diff --git a/drivers/irqchip/irq-riscv-imsic-state.h b/drivers/irqchip/irq-riscv-imsic-state.h index c42ee180b305..11352f14e32d 100644 --- a/drivers/irqchip/irq-riscv-imsic-state.h +++ b/drivers/irqchip/irq-riscv-imsic-state.h @@ -49,6 +49,7 @@ struct imsic_priv { /* Global configuration common for all HARTs */ struct imsic_global_config global; + phys_addr_t *smode_msi_pa; /* Per-CPU state */ struct imsic_local_priv __percpu *lpriv; -- 2.43.0 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv