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From: Junhui Liu <junhui.liu@pigmoral.tech>
To: Daniel Lezcano <daniel.lezcano@kernel.org>,
	 Thomas Gleixner <tglx@kernel.org>, Rob Herring <robh@kernel.org>,
	 Krzysztof Kozlowski <krzk+dt@kernel.org>,
	 Conor Dooley <conor+dt@kernel.org>, Yixun Lan <dlan@kernel.org>,
	 Inochi Amaoto <inochiama@outlook.com>,
	Radu Rendec <radu@rendec.net>,  Paul Walmsley <pjw@kernel.org>,
	Samuel Holland <samuel.holland@sifive.com>,
	 Palmer Dabbelt <palmer@dabbelt.com>,
	Anup Patel <anup@brainfault.org>,
	 Guodong Xu <docular.xu@gmail.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	 Alexandre Ghiti <alex@ghiti.fr>
Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
	 linux-riscv@lists.infradead.org, spacemit@lists.linux.dev,
	 Conor Dooley <conor.dooley@microchip.com>,
	 Junhui Liu <junhui.liu@pigmoral.tech>
Subject: [PATCH v2 0/6] spacemit: k3: Replace bad CLINT node with ACLINT nodes
Date: Wed, 09 Sep 2026 00:28:43 +0800	[thread overview]
Message-ID: <20260909-k3-aclint-v2-0-7931e5bc86ad@pigmoral.tech> (raw)

When testing OpenSBI with the upstream Device Tree, the CLINT controller
failed to function properly with the irqchip.riscv_imsic_noipi boot
parameter:

  Platform IPI Device         : aclint-mswi
  Platform Timer Device       : aclint-mtimer @ 24000000Hz
  
  Domain0 Region03            : 0x00000000e081c000-0x00000000e081ffff M: (I,R,W) S/U: ()
  
  [    0.091014] smp: Bringing up secondary CPUs ...
  [   10.104917] CPU1 failed to report alive state
  [   20.118689] CPU2 failed to report alive state
  [   30.132288] CPU3 failed to report alive state
  [   40.145953] CPU4 failed to report alive state
  [   50.159604] CPU5 failed to report alive state
  [   60.173212] CPU6 failed to report alive state
  [   70.186981] CPU7 failed to report alive state
  [   70.191411] smp: Brought up 1 node, 1 CPU

Through exploring and testing, I discovered that the K3 actually
provides all three complete ACLINT components, and subsequent
confirmation with the vendor yielded the following information:

The ACLINT controllers are mapped to two physical memory regions:
secure (0xf1810000-0xf1820000) and non-secure (0xe0810000-0xe0820000),
with varying accessibility per controller and execution mode:

+---------+--------+------------------------+-----------------------+
| Offset  | Module | Secure Region          | Non-Secure Region     |
+---------+--------+------------------------+-----------------------+
| +0x0000 | MSWI   | 0xf1810000-0xf1813fff  | 0xe0810000-0xe0813fff |
|         |        | (M-mode only)          | (Inaccessible)        |
+---------+--------+------------------------+-----------------------+
| +0x4000 | MTIMER | 0xf1814000-0xf181bfff  | 0xe0814000-0xe081bfff |
|         |        | (M-mode only)          | (Inaccessible)        |
+---------+--------+------------------------+-----------------------+
| +0xc000 | SSWI   | 0xf181c000-0xf181ffff  | 0xe081c000-0xe081ffff |
|         |        | (M-mode only if efused)| (M/S-mode Accessible) |
+---------+--------+------------------------+-----------------------+

Taking these constraints into account, we choose the secure region
(0xf1810000-0xf181bfff) for the M-mode ACLINT components (MSWI and
MTIMER), and the non-secure region (0xe081c000-0xe081ffff) for the
S-mode SSWI component.

Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
---
Changes in v2:
- Drop the generic riscv,aclint-* fallback compatibles and use only
  SpacemiT K3-specific compatibles.
- Match spacemit,k3-aclint-sswi directly in the SSWI driver.
- Squash the ACLINT MSWI and MTIMER DT additions into the patch that
  replaces the incorrect CLINT node.
- Link to v1: https://patch.msgid.link/20260729-k3-aclint-v1-0-aef88614d3a5@pigmoral.tech

---
Junhui Liu (6):
      dt-bindings: timer: thead,c900-aclint-mtimer: Add SpacemiT K3
      dt-bindings: interrupt-controller: thead,c900-aclint-mswi: Add SpacemiT K3
      dt-bindings: interrupt-controller: thead,c900-aclint-sswi: Add SpacemiT K3
      dt-bindings: timer: sifive,clint: Deprecate spacemit,k3-clint
      irqchip/aclint-sswi: Add support for SpacemiT K3
      riscv: dts: spacemit: k3: Replace incorrect CLINT node with ACLINT nodes

 .../thead,c900-aclint-mswi.yaml                    |  1 +
 .../thead,c900-aclint-sswi.yaml                    |  5 +--
 .../devicetree/bindings/timer/sifive,clint.yaml    |  5 ++-
 .../bindings/timer/thead,c900-aclint-mtimer.yaml   |  1 +
 arch/riscv/boot/dts/spacemit/k3.dtsi               | 37 ++++++++++++++++------
 drivers/irqchip/irq-aclint-sswi.c                  |  1 +
 6 files changed, 37 insertions(+), 13 deletions(-)
---
base-commit: cee9395acd8043be0644b25c34bfa86623f2b935
change-id: 20260729-k3-aclint-94ca9d3f818f

Best regards,
--  
Junhui Liu <junhui.liu@pigmoral.tech>


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             reply	other threads:[~2026-09-08 16:30 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-08 16:28 Junhui Liu [this message]
2026-09-08 16:28 ` [PATCH v2 1/6] dt-bindings: timer: thead,c900-aclint-mtimer: Add SpacemiT K3 Junhui Liu
2026-09-08 17:37   ` Conor Dooley
2026-09-08 16:28 ` [PATCH v2 2/6] dt-bindings: interrupt-controller: thead,c900-aclint-mswi: " Junhui Liu
2026-09-08 17:37   ` Conor Dooley
2026-09-08 16:28 ` [PATCH v2 3/6] dt-bindings: interrupt-controller: thead,c900-aclint-sswi: " Junhui Liu
2026-09-08 17:38   ` Conor Dooley
2026-09-08 16:28 ` [PATCH v2 4/6] dt-bindings: timer: sifive,clint: Deprecate spacemit,k3-clint Junhui Liu
2026-09-08 16:49   ` Conor Dooley
2026-09-08 16:28 ` [PATCH v2 5/6] irqchip/aclint-sswi: Add support for SpacemiT K3 Junhui Liu
2026-09-08 16:28 ` [PATCH v2 6/6] riscv: dts: spacemit: k3: Replace incorrect CLINT node with ACLINT nodes Junhui Liu
2026-09-11  8:43 ` [PATCH v2 0/6] spacemit: k3: Replace bad " Bo Gan

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