From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 27F75C88E75 for ; Tue, 15 Sep 2026 03:29:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=OJ5Vm5mQjWgEGvpGYuU+up14iaMQMLVNL8R9fWr+3XY=; b=JHrc7exP7oD4uV Rtd9J/NrSZGOnV2WAHd5NU90wl5JnG86BPgyIicYChtnpolkQOJKs7RpCyNr+Zm1ThPzjoL7W/CiR Ns8O7/HhQtW/a0nkScqpipe9kjSY/Jkwq47SuTAt4fbACnA++qhAbZ1c0TmYKm4qd/pb+amNcn8qS IiFPSSVOWBji6HaqVeMvWn4J1klWKF7I633c7tgtBzH9jb+jlQvj1J4M2fu1G0EVdqxZWGkNjQhO+ vnFeMr82WlVBWoASIV+JHaJrEVXpSR+ZiVOHEaYfrbKSeDineyqwUZ3kbcTMzT4UNCgw64ie3sjIu 08oZNU3Jct5gwQcwTFDA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.99.1 #2 (Red Hat Linux)) id 1x6Jqw-000000057gj-2zlh; Tue, 15 Sep 2026 03:29:02 +0000 Received: from out199-4.us.a.mail.aliyun.com ([47.90.199.4]) by bombadil.infradead.org with esmtps (Exim 4.99.1 #2 (Red Hat Linux)) id 1x6Jqq-000000057VW-1iEu; Tue, 15 Sep 2026 03:28:59 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1789442932; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=bJah1AVjklnltP+n9003t/Lfq0Y0xBXEyF9SiWfTvEg=; b=R7aj9coyj+ECNvKXzrHQPeEq3QCNcyRqGplccq5vGSKbxGyzw6+WSZlQmLtdphzYeJVlWIAgVlwq/XFwDWBX2BNgPDzjOX6dB1Ix5FqLhUFf0a5D2QGDvRKEQVY4olo56WlypaOpCgHtyDRqYWJMXnKQkE2GGdo97IYhnVniy6A= X-Alimail-AntiSpam: AC=PASS;BC=-1|-1;BR=01201311R161e4;CH=green;DM=||false|;DS=||;FP=0|-1|-1|-1|0|-1|-1|-1;HT=maildocker-contentspam033037026112;MF=fangyu.yu@linux.alibaba.com;NM=1;PH=DS;RN=26;SR=0;TI=SMTPD_---0XB.uvT3_1789442928; Received: from localhost.localdomain(mailfrom:fangyu.yu@linux.alibaba.com fp:SMTPD_---0XB.uvT3_1789442928 cluster:ay36) by smtp.aliyun-inc.com; Tue, 15 Sep 2026 11:28:50 +0800 From: fangyu.yu@linux.alibaba.com To: tomasz.jeznach@linux.dev, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, baolu.lu@linux.intel.com, jroedel@suse.de, zong.li@sifive.com, andrew.jones@oss.qualcomm.com, anup@brainfault.org, jgg@nvidia.com, jgg@ziepe.ca, kevin.tian@intel.com, atish.patra@linux.dev, skhawaja@google.com, vasant.hegde@amd.com, joerg.roedel@amd.com Cc: fangyu.yu@linux.alibaba.com, guoren@kernel.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org Subject: [RFC PATCH v4 09/10] iommu/riscv: Add dirty tracking support for second-stage domains Date: Tue, 15 Sep 2026 11:28:28 +0800 Message-Id: <20260915032828.11250-10-fangyu.yu@linux.alibaba.com> X-Mailer: git-send-email 2.39.3 (Apple Git-146) In-Reply-To: <20260915032828.11250-1-fangyu.yu@linux.alibaba.com> References: <20260915032828.11250-1-fangyu.yu@linux.alibaba.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260914_202858_697819_F1566CAC X-CRM114-Status: GOOD ( 10.65 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Fangyu Yu Add hardware dirty tracking support for second-stage (iohgatp) domains used in KVM VFIO device pass-through. The RISC-V IOMMU can automatically set the dirty bit in PTEs on write access when DC.tc.GADE is set and the hardware has AMO_HWAD capability. Wire this up to the iommufd dirty tracking interface: - riscv_iommu_set_dirty_tracking(): Always enabled dirty tracking for second-stage domain. - riscv_iommu_dirty_ops: Exposes set_dirty_tracking and the generic page-table read_and_clear_dirty via IOMMU_PT_DIRTY_OPS(riscv_64). - domain_alloc_paging_flags: Assigns dirty_ops to second-stage domains when AMO_HWAD is advertised in hardware capabilities. - riscv_iommu_capable: Reports IOMMU_CAP_DIRTY_TRACKING when AMO_HWAD is present. Signed-off-by: Fangyu Yu --- drivers/iommu/riscv/iommu.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c index f01fd4e2f840..41b593def1f5 100644 --- a/drivers/iommu/riscv/iommu.c +++ b/drivers/iommu/riscv/iommu.c @@ -1352,6 +1352,21 @@ static int riscv_iommu_attach_paging_domain(struct iommu_domain *iommu_domain, return 0; } +static int riscv_iommu_set_dirty_tracking(struct iommu_domain *iommu_domain, + bool enable) +{ + /* + * Always enabled and the dirty bitmap is cleared prior to + * set_dirty_tracking(). + */ + return 0; +} + +static const struct iommu_dirty_ops riscv_iommu_dirty_ops = { + IOMMU_PT_DIRTY_OPS(riscv_64), + .set_dirty_tracking = riscv_iommu_set_dirty_tracking, +}; + static const struct iommu_domain_ops riscv_iommu_paging_domain_ops = { IOMMU_PT_DOMAIN_OPS(riscv_64), .attach_dev = riscv_iommu_attach_paging_domain, @@ -1442,6 +1457,8 @@ riscv_iommu_domain_alloc_paging_flags(struct device *dev, u32 flags, goto err_free; } cfg.common.features |= BIT(PT_FEAT_RISCV_S2); + if (iommu->caps & RISCV_IOMMU_CAPABILITIES_AMO_HWAD) + domain->domain.dirty_ops = &riscv_iommu_dirty_ops; break; default: ret = -EOPNOTSUPP; @@ -1517,9 +1534,13 @@ static struct iommu_group *riscv_iommu_device_group(struct device *dev) static bool riscv_iommu_capable(struct device *dev, enum iommu_cap cap) { + struct riscv_iommu_device *iommu = dev_to_iommu(dev); + switch (cap) { case IOMMU_CAP_CACHE_COHERENCY: return true; + case IOMMU_CAP_DIRTY_TRACKING: + return !!(iommu->caps & RISCV_IOMMU_CAPABILITIES_AMO_HWAD); default: return false; } -- 2.50.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv