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Mon, 21 Sep 2026 04:14:28 -0700 (PDT) Received: from fedora ([61.74.238.173]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-39e6c6dd585sm13438703a91.0.2026.09.21.04.14.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Sep 2026 04:14:28 -0700 (PDT) From: SeungJu Cheon To: Anup Patel Cc: Atish Patra , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Paolo Bonzini , Andrew Jones , Jinyu Tang , Wang Yechao , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, SeungJu Cheon Subject: [PATCH v1 3/5] KVM: riscv: Write-protect G-stage PTEs atomically Date: Mon, 21 Sep 2026 20:14:00 +0900 Message-ID: <20260921111402.120911-4-suunj1331@gmail.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260921111402.120911-1-suunj1331@gmail.com> References: <20260921111402.120911-1-suunj1331@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260921_121430_954319_FA7AF9C6 X-CRM114-Status: GOOD ( 11.41 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org GSTAGE_OP_WP clears the W bit with a read-modify-write of the entire PTE. Lockless aging can concurrently clear the Accessed bit, allowing write-protection to overwrite the update with a stale PTE value. Clear W atomically with test_and_clear_bit() so that concurrent Accessed-bit updates are preserved. Its return value also preserves the existing behavior of requesting a TLB flush only when W was actually cleared. Signed-off-by: SeungJu Cheon --- arch/riscv/kvm/gstage.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/arch/riscv/kvm/gstage.c b/arch/riscv/kvm/gstage.c index 944fa4c95aea..f7e4756ce15b 100644 --- a/arch/riscv/kvm/gstage.c +++ b/arch/riscv/kvm/gstage.c @@ -378,7 +378,7 @@ bool kvm_riscv_gstage_op_pte(struct kvm_gstage *gstage, gpa_t addr, pte_t *ptep, u32 ptep_level, enum kvm_riscv_gstage_op op) { int i, ret; - pte_t old_pte, pte, *next_ptep; + pte_t pte, *next_ptep; u32 next_ptep_level; unsigned long next_page_size, page_size; bool flush = false; @@ -408,13 +408,16 @@ bool kvm_riscv_gstage_op_pte(struct kvm_gstage *gstage, gpa_t addr, if (op == GSTAGE_OP_CLEAR) put_page(virt_to_page(next_ptep)); } else { - old_pte = *ptep; - if (op == GSTAGE_OP_CLEAR) + if (op == GSTAGE_OP_CLEAR) { set_pte(ptep, __pte(0)); - else if (op == GSTAGE_OP_WP) - set_pte(ptep, __pte(pte_val(ptep_get(ptep)) & ~_PAGE_WRITE)); - if (pte_val(*ptep) != pte_val(old_pte)) flush = true; + } else if (op == GSTAGE_OP_WP) { + /* + * Clear W atomically to avoid clobbering a concurrent + * Accessed-bit update by lockless aging. + */ + flush = test_and_clear_bit(__ffs(_PAGE_WRITE), &ptep->pte); + } } return flush; -- 2.52.0 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv