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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Sat, Oct 03, 2026 at 02:03:35PM +0200, Andrew Jones wrote: > > Hi Robin, > > On Fri, Oct 02, 2026 at 05:21:18PM +0100, Robin Murphy wrote: > > You already end up adding what is effectively a RISC-V-specific > > entrypoint, so you may as well just carry that all the way through to > > its own effectively RISC-V-specific implementation > > The list API came out of the v4[1] discussion with Jason. Preparing the > targets as one contiguous IOVA range lets the MSI descriptor cache the > base and IMSIC compose the address as base + CPU offset. That got > rid of the separate domain-local lookup table and its lifetime handling, > which I think was a worthwhile improvement. Yeah, I prefer this idea to what you had earlier, however it is accomodated. > > it should merely be a case of whether a) this is the first call for > > the given cookie so everything needs mapping, or b) it's not the > > first call, so everything must already be mapped and we can just > > return the IOVA. > > For DMA-IOMMU, yes, remembering the base would let us drop the range > matching. We'd still need the contiguous IOVA allocation, mapping loop, > rollback on failure, and locking across the whole operation. I fell like dma-iommu should have a way to map a page list to iova and maybe that is all the shared code with arm there is. Jason _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv