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[180.177.138.120]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-cd6a85c6fbesm656992a12.11.2026.10.21.04.00.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Oct 2026 04:00:06 -0700 (PDT) From: Hung-Chun Tseng To: Yixun Lan Cc: E Shattow , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 2/2] riscv: dts: spacemit: mark K1 board boot devices bootph-pre-ram Date: Wed, 21 Oct 2026 18:59:59 +0800 Message-ID: <20261021110001.2905669-1-alan.tseng.cs@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261021083425-GKA125937@kernel.org> References: <20261017180141.3477743-3-alan.tseng.cs@gmail.com> <13d6926f-f085-4214-8051-7bf7b5d92b67@freeshell.de> <20261019141752.2077207-1-alan.tseng.cs@gmail.com> <20261021083425-GKA125937@kernel.org> X-Archived-By: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261021_040009_099860_723C9208 X-CRM114-Status: UNSURE ( 9.18 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -2.1 (--) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" X-Spam-Status: No, score=-3.8 required=3.0 tests=BAYES_00,DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=no autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 Hi Yixun, Yixun Lan wrote: > but for bootph-pre-ram, isn't it about the DT nodes which needed before DDR > initialization in SPL stage, and should have nothing to do with BootROM? Thanks for checking with the vendor. I agree, the schema defines it as "the phase that sets up SDRAM". I also need to correct what I said earlier: the EEPROM is not only used to tell the boards apart. It also holds the board's DRAM configuration (number of chip selects, data rate and DDR type), which has to be read before DRAM can be trained [1]. So in v3 I'd like to keep the i2c2 and EEPROM tags, and also tag the EEPROM on the OrangePi RV2 and R2S, which I missed in v2. E, does that address your concern? [1] board/spacemit/k1/spl.c in U-Boot, ddr_early_init() -> read_ddr_info() Thanks, Hung-Chun _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv