From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (prime256v1) server-digest SHA256) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D46E6606A33A for ; Thu, 22 Oct 2026 15:46:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key, unprotected) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=bombadil.20210309 header.b=rBbHdSO9; dkim=fail reason="signature verification failed" (1024-bit key, unprotected) header.d=linux.dev header.i=@linux.dev header.a=rsa-sha256 header.s=key1 header.b=B+kj81o2 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Unsubscribe-Post:List-Owner; bh=sBnQuIddhHFoJwakTiTNhM9UYxT/DqgHFPnx1YO6yOw=; b=rBbHdSO9F2PleeyapX+SGszAt9 lasQjHMkhd/GDjYADJD9Rx6o9ej9LSK1uK24YInB/IGii/dWNBoqp+Ob2RZhF166dDHGixonIEZGw +LGi2+BYNOPHH92zsUI2JTBTHZu+2rHBUlSuFOEfOxLke6moOvh85WLaLf3M6W59xTF+M78NbP/df Gp/WOpYrjVfSXACITJkt6hYj6MPllQFg4x4YP8/2y8zYrVxHqEUl6HplDc1RAbVmkLF/1cB3AmzdB YtC4w/C33yVrFaqb2rGtycU7OKzLnTT3AUtwLfq6taN46U1gp7SJ5DRVj1jArKrI7hylsOwcYYSP+ DFCNpdQQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.100.1 #2 (Red Hat Linux)) id 1xJuzi-0000000EQkw-3qAj; Thu, 22 Oct 2026 15:46:21 +0000 Received: from out-84.mta1.migadu.com ([2001:41d0:203:375::54] helo=mta1.migadu.com) by bombadil.infradead.org with esmtps (Exim 4.100.1 #2 (Red Hat Linux)) id 1xJuze-0000000EQju-24BE for linux-riscv@lists.infradead.org; Thu, 22 Oct 2026 15:46:16 +0000 X-Envelope-To: linux-riscv@lists.infradead.org DKIM-Signature: a=rsa-sha256; bh=K5gk0WLO40R0B55fjMwPkib7g20hUay4hoQc0CNZhRc=; c=simple/simple; d=linux.dev; h=from:to:subject:date:message-id:mime-version:content-type; s=key1; t=1792683972; v=1; x=1793288772; b=B+kj81o2//KNWFTqLM7RV16zmXrceknJUmtuPZVTnsrtWyQReLBYpG/GusMbUT+fAAflh0PC f7yJhqwDa8KGBcbm74Hksm0nGr8fPCMHpVed/oPxjimJT390tdN3gtjm0Q++gxh2u5wWCYRJrZE XFP27JgSwu4H+PG0vnJgJjMQ= X-Envelope-To: linux-riscv@lists.infradead.org Received: by smtp.migadu.com with ESMTPS id 131368cd1c1280cc; Thu, 22 Oct 2026 15:46:12 +0000 X-Mizu-Trace-ID: 131368cd1c1280cc X-Migadu-Flow: FLOW_OUT From: Andrew Jones To: linux-riscv@lists.infradead.org, iommu@lists.linux.dev Cc: linux-kernel@vger.kernel.org, tomasz.jeznach@linux.dev, jgg@ziepe.ca, jgg@nvidia.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, anup@brainfault.org, tglx@kernel.org, kevin.tian@intel.com, fangyu.yu@linux.alibaba.com, nutty.liu@hotmail.com Subject: [PATCH v7 0/5] iommu/riscv: Enable MSI remapping and IOMMU_DMA Date: Thu, 22 Oct 2026 17:45:58 +0200 Message-ID: <20261022154603.1374754-1-andrew.jones@linux.dev> X-Mailer: git-send-email 2.56.0 X-Archived-By: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261022_084614_674001_3C446AFA X-CRM114-Status: GOOD ( 12.46 ) X-Spam-Score: -2.1 (--) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" X-Spam-Status: No, score=-11.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 This series adds MSI remapping for IMSIC so a device's MSI target gets translated the same way its DMA does, allowing RISC-V to enable IOMMU_DMA and paging domains by default. The IMSIC MSI target address changes with interrupt affinity, so every possible target must be mapped before an affinity change can select it in atomic context. The IMSIC driver prepares an ordered list of targets with iommu_dma_prepare_msi_list() when allocating an IRQ. DMA-IOMMU maps the list into one contiguous IOVA range and caches the base in the domain. The MSI descriptor carries the base IOVA and mapping granule, allowing IMSIC to compose the target address without allocating memory or looking up IOMMU state during affinity changes. Ordered-list mappings have their own cache, separate from the existing single-page MSI cache. IOVA allocation, mapping and rollback are shared between the two paths. VFIO and iommufd support from v6[1] is deferred. This series does not enable VFIO_IOMMU_TYPE1 or introduce an IOMMU_RESV_SW_MSI reservation. I'll look into Nicolin's MSI-window configuration patches[2] in a follow-on series and see if I can avoid introducing IOMMU_RESV_SW_MSI entirely. Without that reservation, the legacy Type1 backend cannot provide the MSI mappings it needs, so I'll try to support existing Type1 userspace through iommufd's compatibility interface. That path will need automatic MSI IOVA allocation, since existing Type1 userspace won't issue Nicolin's new ioctls. LLM-based coding assistants were used during development for code exploration, patch review, test execution, and drafting and editing commit messages and this cover letter. I reviewed and finalized all resulting code and text. Per-patch Assisted-by tags are omitted in light of ongoing discussions about simplifying coding-assistant attribution. Thanks, drew [1] https://lore.kernel.org/all/20260925151659.419512-1-andrew.jones@oss.qualcomm.com/ [2] https://lore.kernel.org/linux-iommu/cover.1760487869.git.nicolinc@nvidia.com/ v7: - Rebased on linux-iommu/next at 20bfd2575765 - Added deferred-attach handling to the list API - Simplified ordered-list mapping to a cached base IOVA per domain, separate from the existing per-page cache [Robin] - Shared IOVA allocation, mapping and rollback between the list and single-page paths [Jason] - Dropped the fixed MSI window in response to Jason's ABI concerns and deferred supporting VFIO Type1 Andrew Jones (4): iommu/dma: Prepare MSI physical address lists iommu/dma: Introduce iommu_dma_prepare_msi_list() irqchip/riscv-imsic: Add MSI address list irqchip/riscv-imsic: Support IOMMU MSI address lists Tomasz Jeznach (1): iommu/dma: Enable IOMMU_DMA for 64-bit RISC-V drivers/iommu/Kconfig | 2 +- drivers/iommu/dma-iommu.c | 77 ++++++++++++++++++++-- drivers/iommu/dma-iommu.h | 10 +++ drivers/iommu/iommu.c | 43 ++++++++++++ drivers/irqchip/Kconfig | 1 + drivers/irqchip/irq-riscv-imsic-platform.c | 24 ++++++- drivers/irqchip/irq-riscv-imsic-state.c | 32 +++++++++ drivers/irqchip/irq-riscv-imsic-state.h | 3 + include/linux/iommu.h | 9 +++ 9 files changed, 190 insertions(+), 11 deletions(-) -- 2.56.0 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv