From: E Shattow <e@freeshell.de>
To: Anirudh Srinivasan <asrinivasan@oss.tenstorrent.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>, Yixun Lan <dlan@kernel.org>,
Troy Mitchell <troy.mitchell@linux.spacemit.com>,
Paul Walmsley <pjw@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alex@ghiti.fr>,
Guodong Xu <docular.xu@gmail.com>
Cc: E Shattow <e@freeshell.de>,
devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
spacemit@lists.linux.dev, linux-kernel@vger.kernel.org
Subject: [PATCH] riscv: dts: spacemit: k3: enable status of mimsic and maplic to okay
Date: Thu, 29 Oct 2026 09:23:35 -0700 [thread overview]
Message-ID: <20261029162343.1896134-1-e@freeshell.de> (raw)
Change the "reserved" status of mimsic and maplic to "okay". There is
an mainline OpenSBI user of this and setting status okay resolves the
stall of Linux when probing peripherals at boot.
Fixes: 56f37e391a62 ("riscv: dts: spacemit: add initial support for K3 SoC")
Signed-off-by: E Shattow <e@freeshell.de>
---
Follows a discussion changing the status at U-Boot mailing list:
https://lore.kernel.org/u-boot/20261028184526.1887640-2-e@freeshell.de/
Moving the discussion to LKML as there are differences of opinion on
whether this should be changed in Linux or let remain to downstream
users changing this in firmware that requires it. The change is
trivial to carry downstream in mainline U-Boot.
---
arch/riscv/boot/dts/spacemit/k3.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi
index a5fb72e23dcf..4b3362b64e26 100644
--- a/arch/riscv/boot/dts/spacemit/k3.dtsi
+++ b/arch/riscv/boot/dts/spacemit/k3.dtsi
@@ -1452,7 +1452,7 @@ mimsic: interrupt-controller@f1000000 {
msi-controller;
riscv,hart-index-bits = <4>;
riscv,num-ids = <511>;
- status = "reserved";
+ status = "okay";
};
maplic: interrupt-controller@f1800000 {
@@ -1464,7 +1464,7 @@ maplic: interrupt-controller@f1800000 {
riscv,children = <&saplic>;
riscv,delegation = <&saplic 1 512>;
riscv,num-sources = <512>;
- status = "reserved";
+ status = "okay";
};
aclint_mswi: interrupt-controller@f1810000 {
base-commit: c339f4010dea8b0d754f84ace70cd1b089878ef8
--
2.53.0
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reply other threads:[~2026-10-29 16:24 UTC|newest]
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