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[108.26.179.17]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-462ff3df534sm51691451cf.10.2024.11.10.13.15.53 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 10 Nov 2024 13:15:54 -0800 (PST) Message-ID: <208f8a06-c176-4377-8255-7800ecd2cf6c@gmail.com> Date: Sun, 10 Nov 2024 16:15:53 -0500 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH for-next v2] riscv: Fix default misaligned access trap To: Charlie Jenkins , Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: Palmer Dabbelt , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org References: <20241108-fix_handle_misaligned_load-v2-1-91d547ce64db@rivosinc.com> Content-Language: en-US From: Jesse Taube In-Reply-To: <20241108-fix_handle_misaligned_load-v2-1-91d547ce64db@rivosinc.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241110_131557_015429_BEF8C14D X-CRM114-Status: GOOD ( 13.30 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On 11/8/24 18:47, Charlie Jenkins wrote: > Commit d1703dc7bc8e ("RISC-V: Detect unaligned vector accesses > supported") removed the default handlers for handle_misaligned_load() > and handle_misaligned_store(). When the kernel is compiled without > RISCV_SCALAR_MISALIGNED, these handlers are never defined, causing > compilation errors. > > Signed-off-by: Charlie Jenkins Reviewed-by: Jesse Taube Thanks, Jesse > Fixes: d1703dc7bc8e ("RISC-V: Detect unaligned vector accesses supported") > --- > Changes in v2: > - Change CONFIG_RISCV_SCALAR_MISALIGNED to CONFIG_RISCV_MISALIGNED > (Jesse) > - Link to v1: https://lore.kernel.org/r/20241107-fix_handle_misaligned_load-v1-1-07d7852c9991@rivosinc.com > --- > arch/riscv/include/asm/entry-common.h | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > diff --git a/arch/riscv/include/asm/entry-common.h b/arch/riscv/include/asm/entry-common.h > index 7b32d2b08bb6..b28ccc6cdeea 100644 > --- a/arch/riscv/include/asm/entry-common.h > +++ b/arch/riscv/include/asm/entry-common.h > @@ -25,7 +25,19 @@ static inline void arch_exit_to_user_mode_prepare(struct pt_regs *regs, > void handle_page_fault(struct pt_regs *regs); > void handle_break(struct pt_regs *regs); > > +#ifdef CONFIG_RISCV_MISALIGNED > int handle_misaligned_load(struct pt_regs *regs); > int handle_misaligned_store(struct pt_regs *regs); > +#else > +static inline int handle_misaligned_load(struct pt_regs *regs) > +{ > + return -1; > +} > + > +static inline int handle_misaligned_store(struct pt_regs *regs) > +{ > + return -1; > +} > +#endif > > #endif /* _ASM_RISCV_ENTRY_COMMON_H */ > > --- > base-commit: 74741a050b79d31d8d2eeee12c77736596d0a6b2 > change-id: 20241107-fix_handle_misaligned_load-8be86cb0806e _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv