From: "Rémi Denis-Courmont" <remi@remlab.net>
Cc: linux-riscv@lists.infradead.org
Subject: Re: [PATCH v2 3/3] RISC-V: add T-Head vector errata handling
Date: Tue, 27 Jun 2023 18:21:14 +0300 [thread overview]
Message-ID: <2285267.ElGaqSPkdT@basile.remlab.net> (raw)
In-Reply-To: <20230622231305.631331-4-heiko@sntech.de>
Le perjantaina 23. kesäkuuta 2023, 2.13.05 EEST Heiko Stuebner a écrit :
> From: Heiko Stuebner <heiko.stuebner@vrull.eu>
>
> T-Head C9xx cores implement an older version (0.7.1) of the vector
> specification.
>
> Relevant changes concerning the kernel are:
> - different placement of the SR_VS bit for the vector unit status
> - different encoding of the vsetvli instruction
> - different instructions for loads and stores
>
> And a fixed VLEN of 128.
Ultimately, conformant hardware also has a fixed VLEN of some value.
So why is that relevant here? is the vlenb CSR not implemented? And even if
so, c the value not be retrieved with vsetvli?
--
Rémi Denis-Courmont
http://www.remlab.net/
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next prev parent reply other threads:[~2023-06-27 15:21 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-22 23:13 [PATCH v2 0/2] RISC-V: T-Head vector handling Heiko Stuebner
2023-06-22 23:13 ` [PATCH v2 1/3] RISC-V: define the elements of the VCSR vector CSR Heiko Stuebner
2023-06-22 23:13 ` [PATCH v2 2/3] RISC-V: move vector-available status into a dedicated variable Heiko Stuebner
2023-06-23 9:19 ` Conor Dooley
2023-06-23 13:47 ` kernel test robot
2023-06-22 23:13 ` [PATCH v2 3/3] RISC-V: add T-Head vector errata handling Heiko Stuebner
2023-06-23 3:11 ` kernel test robot
2023-06-23 9:49 ` Conor Dooley
2023-06-23 10:40 ` Heiko Stübner
2023-06-23 11:44 ` Conor Dooley
2023-06-24 5:18 ` Stefan O'Rear
2023-06-24 10:59 ` Andrew Jones
2023-06-28 16:07 ` Andy Chiu
2023-06-23 13:47 ` kernel test robot
2023-06-27 15:21 ` Rémi Denis-Courmont [this message]
2023-06-27 16:12 ` Conor Dooley
2023-06-28 14:23 ` Palmer Dabbelt
2023-06-29 16:06 ` Rémi Denis-Courmont
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