From: Kefeng Wang <wangkefeng.wang@huawei.com>
To: Christoph Hellwig <hch@infradead.org>
Cc: <palmerdabbelt@google.com>, <paul.walmsley@sifive.com>,
<palmer@dabbelt.com>, <linux-riscv@lists.infradead.org>
Subject: Re: [PATCH 1/3] riscv: Allow forced irq threading
Date: Thu, 8 Jul 2021 14:42:45 +0800 [thread overview]
Message-ID: <231ce61f-1af6-dea0-bcdb-a8de3c42a3fa@huawei.com> (raw)
In-Reply-To: <YOaM9bfqZiU386T7@infradead.org>
On 2021/7/8 13:28, Christoph Hellwig wrote:
> On Thu, Jul 08, 2021 at 09:59:47AM +0800, Kefeng Wang wrote:
>> The timer interrupt and the perf interrupt on riscv are with
>> IRQF_PERCPU, so it's safe to allow forced interrupt threading.
> "Architecture code needs to select CONFIG_IRQ_FORCED_THREADING after
> marking the interrupts which cant be threaded IRQF_NO_THREAD.
> All interrupts which have IRQF_TIMER set are implict marked
> IRQF_NO_THREAD. Also all PER_CPU interrupts are excluded."
>
> Did you do that audit?
Yes, I check the perf and timer on RISCV,
arch/riscv/kernel/perf_event.c
static int reserve_pmc_hardware(void)
{
err = request_irq(riscv_pmu->irq, riscv_pmu->handle_irq,
IRQF_PERCPU, "riscv-base-perf", NULL);
}
drivers/clocksource/timer-riscv.c
static int __init riscv_timer_init_dt(struct device_node *n)
{
error = request_percpu_irq(riscv_clock_event_irq,
riscv_timer_interrupt,
"riscv-timer", &riscv_clock_event);
}
Is this enough?
> .
>
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next prev parent reply other threads:[~2021-07-08 6:43 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-08 1:59 [PATCH 0/3] riscv: Enable some feature for RISCV Kefeng Wang
2021-07-08 1:59 ` [PATCH 1/3] riscv: Allow forced irq threading Kefeng Wang
2021-07-08 5:28 ` Christoph Hellwig
2021-07-08 6:42 ` Kefeng Wang [this message]
2021-08-04 20:33 ` Palmer Dabbelt
2021-07-08 1:59 ` [PATCH 2/3] riscv: Enable idle generic idle loop Kefeng Wang
2021-07-08 1:59 ` [PATCH 3/3] riscv: Enable GENERIC_IRQ_SHOW_LEVEL Kefeng Wang
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