From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3DFDFC433F5 for ; Tue, 11 Oct 2022 07:59:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=WtMmVMwWAgQnJlebO+NwRj1ScNRMN5BS9pOhWXD9yFo=; b=Gc6PhFyK9MCZ4p ihEvmi12NhQMkGvFzLs9TlxGpYRkdrlPxg2vbS6J29ubNDHux5OzzjjdU1Ija0vjMpG4DOdv6Wudg rQ8OPgBKa8j1ulhewfuuc7qURguYbMISJ9CNi9EcXOZbZ3PH13Av43WRF6Zabap+tkPBiSkEaOy1E lGmJFqLVzAG4ddntrfRwWjANXTeQbrtD5vjCArzU8RJnL86ZkYWriFZHb5bsve0tVPjTmqDga5IGz TNsUWT7BAs9ij9WSibERhbgjr6G3B510mdp4KwEl/fIM3yj5yGt3SMT5JguaTman2lkX+mZtNVjPf +LJCKrJ1OwmWYf1/FDkw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oiAA7-003eBg-Pf; Tue, 11 Oct 2022 07:58:51 +0000 Received: from gloria.sntech.de ([185.11.138.130]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oiAA5-003eBN-3h for linux-riscv@lists.infradead.org; Tue, 11 Oct 2022 07:58:50 +0000 Received: from p5b127dea.dip0.t-ipconnect.de ([91.18.125.234] helo=phil.localnet) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1oiA9v-0007NI-Qz; Tue, 11 Oct 2022 09:58:39 +0200 From: Heiko Stuebner To: Anup Patel Cc: atishp@atishpatra.org, anup@brainfault.org, will@kernel.org, mark.rutland@arm.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Conor.Dooley@microchip.com, ajones@ventanamicro.com Subject: Re: [PATCH v5 1/2] RISC-V: Cache SBI vendor values Date: Tue, 11 Oct 2022 09:58:38 +0200 Message-ID: <2758592.Sgy9Pd6rRy@phil> In-Reply-To: References: <20221010122726.2405153-1-heiko@sntech.de> <7864901.lvqk35OSZv@phil> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221011_005849_183868_535C5FFD X-CRM114-Status: GOOD ( 30.35 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Hi Anup, Am Montag, 10. Oktober 2022, 15:14:21 CEST schrieb Anup Patel: > On Mon, Oct 10, 2022 at 6:25 PM Heiko Stuebner wrote: > > > > Am Montag, 10. Oktober 2022, 14:45:45 CEST schrieb Anup Patel: > > > On Mon, Oct 10, 2022 at 5:57 PM Heiko Stuebner wrote: > > > > > > > > sbi_get_mvendorid(), sbi_get_marchid() and sbi_get_mimpid() might get > > > > called multiple times, though the values of these CSRs should not change > > > > during the runtime of a specific machine. > > > > > > > > So cache the values in the functions and prevent multiple ecalls > > > > to read these values. > > > > > > > > As Andrew Jones noted, at least marchid and mimpid may be negative > > > > values when viewed as a long, so we use a separate static bool to > > > > indiciate the cached status. > > > > > > > > Suggested-by: Atish Patra > > > > Signed-off-by: Heiko Stuebner > > > > --- > > > > arch/riscv/kernel/sbi.c | 30 +++++++++++++++++++++++++++--- > > > > 1 file changed, 27 insertions(+), 3 deletions(-) > > > > > > > > diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c > > > > index 775d3322b422..cc618aaa9d11 100644 > > > > --- a/arch/riscv/kernel/sbi.c > > > > +++ b/arch/riscv/kernel/sbi.c > > > > @@ -625,17 +625,41 @@ static inline long sbi_get_firmware_version(void) > > > > > > > > long sbi_get_mvendorid(void) > > > > { > > > > - return __sbi_base_ecall(SBI_EXT_BASE_GET_MVENDORID); > > > > + static long id; > > > > + static bool cached; > > > > + > > > > + if (!cached) { > > > > + id = __sbi_base_ecall(SBI_EXT_BASE_GET_MVENDORID); > > > > + cached = true; > > > > + } > > > > + > > > > + return id; > > > > } > > > > > > > > long sbi_get_marchid(void) > > > > { > > > > - return __sbi_base_ecall(SBI_EXT_BASE_GET_MARCHID); > > > > + static long id; > > > > + static bool cached; > > > > > > This breaks for heterogeneous SMP systems (similar to big.LITTLE) > > > where HARTs will have different marchid even though they belong to > > > same CPU Vendor. > > > > > > Due to the above rationale, the patch adding marchid, mvendorid, and > > > mimpid in /proc/cpuinfo caches these values on a per-CPU basis. > > > > For people reading along, I think you mean > > https://lore.kernel.org/r/20220727043829.151794-1-apatel@ventanamicro.com > > Yes, this is the patch I am referring. > > > > > For my understanding, was there a reason in the past for doing the caching > > only for cpuinfo and not for every invocation of the ecalls? > > The caching was done only for /proc/cpuinfo because at that point > time only "cat /proc/cpuinfo" would need these value at runtime. > > Now that we have more uses of marchid, mvendorid, and mimpid, > at runtime, we should definitely have the cached values available > to other parts of kernel. > > My suggestion is to keep sbi_get_xyz() functions unmodified and > instead add new functions in arch/riscv/kernel/cpu.c (on-top-of > /proc/cpuinfo patch) which allows users to read cached values of > any CPU. > > For example, we could export following functions from > arch/riscv/kernel/cpu.c: > unsigned long riscv_cached_mvendorid(unsigned int cpu); > unsigned long riscv_cached_marchid(unsigned int cpu); > unsigned long riscv_cached_mimpid(unsigned int cpu); sounds sensible, so I'll go that way you suggested :-) Thanks Heiko _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv