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Tue, 16 Dec 2025 21:05:41 +0000 Received: from [IPV6:2001:861:4450:d360:30d8:94c5:9529:bfd5] (unknown [IPv6:2001:861:4450:d360:30d8:94c5:9529:bfd5]) (Authenticated sender: michael.opdenacker@rootcommit.com) by smtp.hostinger.com (smtp.hostinger.com) with ESMTPSA id 4dW8bP3ypjz3wjX; Tue, 16 Dec 2025 21:05:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rootcommit.com; s=hostingermail-a; t=1765919138; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=eTIrfuDhr24TI2lSZux/GGADITfOggiET8mFqMQX6js=; b=UKNLg8pXXoeAuakJeFqoK+ULNQZRigp0iHQY1LrOcj1LlyjCNmZa/LoXXs1IZ9ew6ZEtf8 CmitUHZfOlGgEQxWkOW24iJIV4t7HTyC4EIDLVlPoZAKKt/Ph+i5NFYN99koIyoKrHVQxw FUvjTXQ15UTztak95hzfioMkL8V9XOARENY5qaciTSowv0orteZEjLwUztLKCRPgZj5574 0NH1ETZQuL0xM9ozgK6NaIC9YBerVgMiGP9IT5f9Gzh8c/s1bWvosBT6nEC4yXI/Evunrh 1O3Apw6Y/zWDNXJrgrfJ/Eaxban5rpTixlLwKLWtpmWci6ducINCtiqOE3YBKA== Message-ID: <29600710-fc66-41d0-b399-1b635d0789d9@rootcommit.com> MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Cc: michael.opdenacker@rootcommit.com, Dan Carpenter , Binbin Zhou , linux-riscv@lists.infradead.org, spacemit@lists.linux.dev Subject: Re: [PATCH 1/2] riscv: dts: spacemit: Add i2c buses on OrangePi RV2 To: Yao Zi , Yixun Lan References: <20251215-k1-boards-add-mmc-v1-0-d68dc87d4aab@rootcommit.com> <20251215-k1-boards-add-mmc-v1-1-d68dc87d4aab@rootcommit.com> <4acfc5d8-d8d9-4c9b-99eb-09c7b82ddd04@rootcommit.com> Content-Language: en-US, fr From: Michael Opdenacker Organization: Root Commit In-Reply-To: Date: Tue, 16 Dec 2025 21:05:37 +0000 (UTC) X-CM-Envelope: MS4xfF5Vy1L1KouG49QIlLe5kFFaXNS6TCn6EH+qUk1Sff+7pUTB5PALKx2/986sedZ/CpYlJBEMbNbEqnJGpcWbKwcczUoTHni66kVNztVM/R7p0sglBT36 CSkRnhk3RJfH19FzmLnZ8Tr0MsCqFvusJ5Ipxjm5YhyAwvdsiBNMw91oU82GVtWgRjzJBgxvXtdfh9432MU6siiFl4qIXC6/iqNQJGU1laDfeiyeVueY3lPS u8OMRNJv1OmnNOsFunYZU1370GGSNSsaPgu0/IwogzSzPftmpXcSzBf5mcl8+1rST5OHM/ldHIvgMc76gzmJWcI8B+QjfpUEwlNqRL/q9/EokhoHNJqX+o0I H4/08Z0UKHie0MFEc4dekOiCwfL2uH0kPDVavoRMfrs+JgKLRG4qS70nlCXD/vGkykHPkQa2SKp36XiX5zKYRnjddJqUaL/EJ9W8MTDr2s3QHR5nnMwTktOG S9WrGF8kLnZ1JTw6QMEkPnc9hiAmZFh+jNTHqEfdZTmw2XvBQYi/icN9qQo= X-CM-Analysis: v=2.4 cv=Ceda56rl c=1 sm=1 tr=0 ts=6941c9a2 a=txFWH1vTMWaEHP0dv8CF8Q==:617 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=lv0vYI88AAAA:8 a=d70CFdQeAAAA:8 a=VJnbNgQhEQg3sspumF4A:9 a=QEXdDO2ut3YA:10 a=9qqun4PRrEabIEPCFt1_:22 a=NcxpMcIZDGm-g932nG_k:22 X-AuthUser: michael.opdenacker@rootcommit.com X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20251216_130545_167729_443AE817 X-CRM114-Status: GOOD ( 32.81 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Hi Yao Thanks a lot for your help and tips, much appreciated! On 12/16/25 06:37, Yao Zi wrote: > On Mon, Dec 15, 2025 at 03:00:52PM +0000, Michael Opdenacker wrote: >> Hi Yao >> >> Thanks for your helpful questions! >> >> On 12/15/25 13:58, Yao Zi wrote: >>> On Mon, Dec 15, 2025 at 10:10:14AM +0000, Michael Opdenacker wrote: >>>> The OrangePi RV2 board exposes i2c2 and i2c8 buses >>>> from the Spacemit K1 SoC. >>>> >>>> This declares devices present on such buses, in particular >>>> the at24 eeprom to store MAC addresses and the regulators >>>> attached to the PMIC on i2c8. >>> This series is named as "Attempt to enable MMC on SpacemiT K1 boards", >>> what's the relationship between MMC and PMIC/I2C bus? You didn't make >>> use of any regulators in the second patch, either (which seems wrong to >>> me). >> I expected that declaring the regulators under the PMIC on i2c8 was enough >> to enable them, but I'm happy to be corrected. > Declaring them doesn't mean enable them. Regulator subsystem maintains a > enable reference count, and when it downcounts to zero, the regulator > gets disabled. > > If no driver acquires one regulator, it gets disabled after 30s since > the regulator subsystem is initialized, see regulator_init_complete() > and regulator_init_complete_work_function. > > On BPI F3, SD is supplied by buck4 of the PMIC. It's marked as > regulator-always-on, so wouldn't be disabled and then cause issues for > the SD card, but this doesn't mean it's okay to omit the correct > regulator supplier of SD. Good to know! Surprisingly, when I add this to the "sdhci0" node: vmmc-supply = <&buck4_3v3>; (after creating the label, of course), the device and its partition no longer show up in /proc/partitions! I was hopeful because read-only mode already seems to work, but maybe indeed things are more complicated. > >>> vmmc-supply specifies the card's power supply. And if you want to enable >>> SDR modes which mandate 1.8v IO level, vqmmc-supply is also necessary >>> for switching between 1.8v and 3.3v. >> >> I was thinking to get started without the SDR modes first, to make sure >> basic operation works first. Would that work? > Yes. > > FYI, for SDR104 mode, you may need to implement some tuning logic[1] as > indicated by vendor driver, > > /* > * Tuning is required for SDR50/SDR104, HS200/HS400 cards and > * if clock frequency is greater than 100MHz in these modes. > */ > > Though in mainline the eMMC on BPI-F3 already makes use of HS400 mode > without tuning. No idea what happened here, or it just happens to work > well. > > Also, the pin controller on K1 SoC seems to have some undocumented > registers to select the IO voltage of SD pins, which should be adjusted > when switching IO voltage[2]. > > I think these pins should be implemented in the pinctrl driver, then you > could create two pinctrl states, one for 1.8v operation, one for 3.3v, > and switch between them through pinctrl_lookup_state() when changing IO > voltage. > > The last thing to mention is that the three MMC controllers on K1 aren't > same, The one used for eMMC is the only one that has a phy (both SD and > SDIO controllers are marked as SDHCI_QUIRK2_BROKEN_PHY_MODULE[3]), thus > have different reset and tuning logics. Wow, that's surprising. https://developer.spacemit.com/documentation?token=WZNvwFDkYinYx0k9jzPcMK5WnIe#12.5-sd%2Femmc doesn't seem to mention this (though I didn't check very carefully yet). > > You probably need to create new compatibles for the SD and SDIO > controllers instead of re-using spacemit,k1-sdhci, and write correct > sdhci_spacemit_reset() for controllers without phy. This is probably > necessary even if you don't implement SDR modes. > >> Would you have board examples to recommend, with an MMC controller operating >> in a way similar to the one on SpacemiT K1? > All sd/emmc controllers work similarly... you may want to take a look at > mmc-controller-common.yaml for common properties. Right, I'm already using it :) I'll be patient and try to progress step by step. My time is quite limited these days, so everyone is welcome to try and make this work. Thanks again for everything Cheers Michael. -- Michael Opdenacker Root Commit Yocto Project and OpenEmbedded Training course - Learn by doing: https://rootcommit.com/training/yocto/ _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv