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Tue, 13 Feb 2024 13:31:12 -0800 (PST) X-Forwarded-Encrypted: i=1; AJvYcCU+BDpt4pBjCo/TnTlQWv/RqyO2ITx8HDD405KDduEgmwpfU99upKZQBNXadPD86wkWEO518ONVRpCM19z3Mggm5L4+2fTCH2q2L7NeRVMflHX4HjAkuguQvFriU5HKvtXBpcYrICdOOVZV6DMMiBp+p8trk4/JBFLJOcLEk/vI0Yd7Awn8tB0tXj/C7hECIhcF Received: from [100.64.0.1] ([170.85.8.192]) by smtp.gmail.com with ESMTPSA id v15-20020a05620a122f00b00785d3729eb0sm2265833qkj.41.2024.02.13.13.31.11 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 13 Feb 2024 13:31:12 -0800 (PST) Message-ID: <2d4d939d-4b49-44d7-8405-e075de844884@sifive.com> Date: Tue, 13 Feb 2024 15:31:10 -0600 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 3/4] riscv/barrier: Consolidate fence definitions Content-Language: en-US To: Eric Chan , paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org References: <20240213200923.2547570-1-ericchancf@google.com> <20240213201210.2549488-1-ericchancf@google.com> From: Samuel Holland In-Reply-To: <20240213201210.2549488-1-ericchancf@google.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240213_133115_859669_D30ADE3A X-CRM114-Status: GOOD ( 13.46 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Hi Eric, On 2024-02-13 2:12 PM, Eric Chan wrote: > Disparate fence implementations are consolidated into fence.h. > Also introduce RISCV_FENCE_ASM to make fence macro more reusable. > > Signed-off-by: Eric Chan > --- > v3 -> v4: fix the form that can pass the checking of checkpatch.pl. > arch/riscv/include/asm/atomic.h | 8 ++------ > arch/riscv/include/asm/barrier.h | 3 +-- > arch/riscv/include/asm/cmpxchg.h | 1 - > arch/riscv/include/asm/fence.h | 10 +++++++--- > arch/riscv/include/asm/io.h | 8 ++++---- > arch/riscv/include/asm/mmio.h | 5 +++-- > arch/riscv/include/asm/mmiowb.h | 2 +- > 7 files changed, 18 insertions(+), 19 deletions(-) > > diff --git a/arch/riscv/include/asm/atomic.h b/arch/riscv/include/asm/atomic.h > index 31e6e2e7cc18..19050d13b6c1 100644 > --- a/arch/riscv/include/asm/atomic.h > +++ b/arch/riscv/include/asm/atomic.h > @@ -17,13 +17,9 @@ > #endif > > #include > -#include > > -#define __atomic_acquire_fence() \ > - __asm__ __volatile__(RISCV_ACQUIRE_BARRIER "" ::: "memory") > - > -#define __atomic_release_fence() \ > - __asm__ __volatile__(RISCV_RELEASE_BARRIER "" ::: "memory"); > +#define __atomic_acquire_fence() RISCV_FENCE(r, rw) > +#define __atomic_release_fence() RISCV_FENCE(rw, r) This change removes the omit-the-fence-on-uniprocessor optimization, like you added some instances of in your previous patch. Should we keep this optimization? Regards, Samuel _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv