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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On 15/05/2026 03:18, Jia Wang via B4 Relay wrote: > + > + cluster0_l3: l3-cache0 { > + /* L3 cache: Use Linux coding style. In other places as well. Even netdev does not use that style anymore! > + * cache-unified, block-size 64B > + * 16-way set associative, size 4MB > + * per-cluster. > + */ > + compatible = "cache"; > + cache-block-size = <64>; > + cache-level = <3>; > + cache-size = <0x400000>; > + cache-sets = <0x1000>; > + cache-unified; > + next-level-cache = <&l4_cache>; > + }; > + > + cluster1_l3: l3-cache1 { > + /* L3 cache: > + * cache-unified, block-size 64B > + * 16-way set associative, size 4MB > + * per-cluster. > + */ > + compatible = "cache"; > + cache-block-size = <64>; > + cache-level = <3>; > + cache-size = <0x400000>; > + cache-sets = <0x1000>; > + cache-unified; > + next-level-cache = <&l4_cache>; > + }; > + }; > + > + clocks { > + device_clk: device_clk { You need to follow DTS coding style. Anyway, something like "device clock" is completely uninformative or even incorrect. I really doubt such thing as "device clock" exists... Please use name for all fixed clocks which matches current format recommendation: 'clock-' (see also the pattern in the binding for any other options). https://web.git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/clock/fixed-clock.yaml > + compatible = "fixed-clock"; > + clock-frequency = <62500000>; > + #clock-cells = <0>; > + }; > + > + timer_clk: timer_clk { > + compatible = "fixed-clock"; > + clock-frequency = <50000000>; > + #clock-cells = <0>; > + }; > + > + csr_clk: csr_clk { > + compatible = "fixed-clock"; > + clock-frequency = <250000000>; > + #clock-cells = <0>; > + }; > + }; > + > + l4_cache: l4-cache { > + /* L4 cache: > + * cache-unified, block-size 64B > + * 16-way set associative, size 16MB > + * shared by the SoC. > + */ > + compatible = "cache"; > + cache-block-size = <64>; > + cache-level = <4>; > + cache-size = <0x1000000>; > + cache-sets = <0x4000>; > + cache-unified; > + }; > + > + memory@80000000 { > + device_type = "memory"; > + reg = <0x00 0x80000000 0x4 0x00000000>; > + }; > + > + soc { > + compatible = "simple-bus"; > + ranges; > + #address-cells = <0x02>; > + #size-cells = <0x02>; <2> This is not hex and definitely does not need padding with 0. > + > + clint: clint@8000000 { > + compatible = "sifive,clint0", "riscv,clint0"; > + reg = <0x00 0x8000000 0x00 0x100000>; > + interrupts-extended = <&cpu0_intc 0x03>, <&cpu0_intc 0x07>, > + <&cpu1_intc 0x03>, <&cpu1_intc 0x07>, > + <&cpu2_intc 0x03>, <&cpu2_intc 0x07>, > + <&cpu3_intc 0x03>, <&cpu3_intc 0x07>, > + <&cpu4_intc 0x03>, <&cpu4_intc 0x07>, > + <&cpu5_intc 0x03>, <&cpu5_intc 0x07>, > + <&cpu6_intc 0x03>, <&cpu6_intc 0x07>, > + <&cpu7_intc 0x03>, <&cpu7_intc 0x07>; > + }; > + > + plic: plic@9000000 { > + compatible = "ultrarisc,dp1000-plic", "ultrarisc,cp100-plic"; > + reg = <0x00 0x9000000 0x00 0x4000000>; > + #interrupt-cells = <1>; > + #address-cells = <0>; So hex or not hex? Please fix your DTS so it is consistent. > + interrupt-controller; > + interrupts-extended = <&cpu0_intc 0xb>, <&cpu0_intc 0x9>, <&cpu0_intc 0xa>, > + <&cpu1_intc 0xb>, <&cpu1_intc 0x9>, <&cpu1_intc 0xa>, > + <&cpu2_intc 0xb>, <&cpu2_intc 0x9>, <&cpu2_intc 0xa>, > + <&cpu3_intc 0xb>, <&cpu3_intc 0x9>, <&cpu3_intc 0xa>, > + <&cpu4_intc 0xb>, <&cpu4_intc 0x9>, <&cpu4_intc 0xa>, > + <&cpu5_intc 0xb>, <&cpu5_intc 0x9>, <&cpu5_intc 0xa>, > + <&cpu6_intc 0xb>, <&cpu6_intc 0x9>, <&cpu6_intc 0xa>, > + <&cpu7_intc 0xb>, <&cpu7_intc 0x9>, <&cpu7_intc 0xa>; > + riscv,ndev = <160>; > + }; > + > + pmx0: pinmux@11081000 { > + compatible = "ultrarisc,dp1000-pinctrl"; > + reg = <0x0 0x11081000 0x0 0x1000>; > + #pinctrl-cells = <2>; > + }; > + > + gpio: gpio@20200000 { > + compatible = "snps,dw-apb-gpio"; > + reg = <0x0 0x20200000 0x0 0x1000>; > + #address-cells = <1>; > + #size-cells = <0>; > + clock-names = "bus", "db"; > + clocks = <&csr_clk>, <&device_clk>; > + > + gpio_a: gpio-port@0 { > + compatible = "snps,dw-apb-gpio-port"; > + reg = <0>; > + gpio-controller; > + #gpio-cells = <2>; > + snps,nr-gpios = <16>; > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupt-parent = <&plic>; > + interrupts = <34>; > + gpio-ranges = <&pmx0 0 0 16>; > + }; > + > + gpio_b: gpio-port@1 { > + compatible = "snps,dw-apb-gpio-port"; > + reg = <1>; > + gpio-controller; > + #gpio-cells = <2>; > + snps,nr-gpios = <8>; > + gpio-ranges = <&pmx0 16 0 8>; > + }; > + > + gpio_c: gpio-port@2 { > + compatible = "snps,dw-apb-gpio-port"; > + reg = <2>; > + gpio-controller; > + #gpio-cells = <2>; > + snps,nr-gpios = <8>; > + gpio-ranges = <&pmx0 24 0 8>; > + }; > + > + gpio_d: gpio-port@3 { > + compatible = "snps,dw-apb-gpio-port"; > + reg = <3>; > + gpio-controller; > + #gpio-cells = <2>; > + snps,nr-gpios = <8>; > + gpio-ranges = <&pmx0 32 0 8>; > + }; > + }; > + > + uart0: serial@20300000 { > + compatible = "ultrarisc,dp1000-uart", "snps,dw-apb-uart"; > + reg = <0x00 0x20300000 0x00 0x10000>; > + interrupt-parent = <&plic>; > + interrupts = <17>; > + clock-frequency = <62500000>; > + reg-io-width = <0x04>; > + reg-shift = <0x02>; > + }; > + > + uart1: serial@20310000 { > + compatible = "ultrarisc,dp1000-uart", "snps,dw-apb-uart"; > + reg = <0x00 0x20310000 0x00 0x10000>; > + interrupt-parent = <&plic>; > + interrupts = <18>; > + clock-frequency = <62500000>; > + reg-io-width = <0x04>; > + reg-shift = <0x02>; > + }; > + > + uart2: serial@20400000 { > + compatible = "ultrarisc,dp1000-uart", "snps,dw-apb-uart"; > + reg = <0x00 0x20400000 0x00 0x10000>; > + interrupt-parent = <&plic>; > + interrupts = <25>; > + clock-frequency = <62500000>; > + reg-io-width = <0x04>; > + reg-shift = <0x02>; > + }; > + > + uart3: serial@20410000 { > + compatible = "ultrarisc,dp1000-uart", "snps,dw-apb-uart"; > + reg = <0x00 0x20410000 0x00 0x10000>; > + interrupt-parent = <&plic>; > + interrupts = <26>; > + clock-frequency = <62500000>; > + reg-io-width = <0x04>; > + reg-shift = <0x02>; > + }; > + > + spi0: spi@20320000 { > + compatible = "snps,dw-apb-ssi"; > + reg = <0x0 0x20320000 0x0 0x1000>; > + #address-cells = <1>; > + #size-cells = <0>; > + clocks = <&device_clk>; > + interrupt-parent = <&plic>; > + interrupts = <19>; > + num-cs = <3>; > + }; > + > + spi1: spi@20420000 { > + compatible = "snps,dw-apb-ssi"; > + reg = <0x0 0x20420000 0x0 0x1000>; > + #address-cells = <1>; > + #size-cells = <0>; > + clocks = <&device_clk>; > + interrupt-parent = <&plic>; > + interrupts = <27>; > + num-cs = <3>; > + }; > + > + i2c0: i2c@20330000 { > + compatible = "snps,designware-i2c"; > + reg = <0x0 0x20330000 0x0 0x100>; > + #address-cells = <1>; > + #size-cells = <0>; > + clock-frequency = <400000>; > + clocks = <&device_clk>; > + interrupt-parent = <&plic>; > + interrupts = <20>; > + }; > + > + i2c1: i2c@20340000 { > + compatible = "snps,designware-i2c"; > + reg = <0x0 0x20340000 0x0 0x100>; > + #address-cells = <1>; > + #size-cells = <0>; > + clock-frequency = <400000>; > + clocks = <&device_clk>; > + interrupt-parent = <&plic>; > + interrupts = <21>; > + }; > + > + i2c2: i2c@20430000 { > + compatible = "snps,designware-i2c"; > + reg = <0x0 0x20430000 0x0 0x100>; > + #address-cells = <1>; > + #size-cells = <0>; > + clock-frequency = <400000>; > + clocks = <&device_clk>; > + interrupt-parent = <&plic>; > + interrupts = <28>; > + }; > + > + i2c3: i2c@20440000 { > + compatible = "snps,designware-i2c"; > + reg = <0x0 0x20440000 0x0 0x100>; > + #address-cells = <1>; > + #size-cells = <0>; > + clock-frequency = <400000>; > + clocks = <&device_clk>; > + interrupt-parent = <&plic>; > + interrupts = <29>; > + }; > + > + pcie_x16: pcie@21000000 { > + compatible = "ultrarisc,dp1000-pcie"; > + reg = <0x0 0x21000000 0x0 0x01000000>, > + <0x0 0x4fff0000 0x0 0x00010000>; > + reg-names = "dbi", "config"; > + ranges = <0x81000000 0x0 0x4fbf0000 0x0 0x4fbf0000 0x0 0x00400000>, > + <0x82000000 0x0 0x40000000 0x0 0x40000000 0x0 0x0fbf0000>, > + <0xc3000000 0x40 0x00000000 0x40 0x00000000 0xd 0x00000000>; > + #address-cells = <3>; > + #size-cells = <2>; > + #interrupt-cells = <1>; > + device_type = "pci"; > + dma-coherent; > + bus-range = <0x0 0xff>; > + num-lanes = <16>; > + interrupt-parent = <&plic>; > + interrupts = <43>, <44>, <45>, <46>, <47>; > + interrupt-names = "msi", "inta", "intb", "intc", "intd"; > + interrupt-map-mask = <0x0 0x0 0x0 0x7>; > + interrupt-map = <0x0 0x0 0x0 0x1 &plic 44>, > + <0x0 0x0 0x0 0x2 &plic 45>, > + <0x0 0x0 0x0 0x3 &plic 46>, > + <0x0 0x0 0x0 0x4 &plic 47>; Why PCIe without any devices is enabled? That's a bus. Please look how other DTS are written because you created something pretty different than entire kernel style. > + }; > + > + pcie_x4a: pcie@23000000 { > + compatible = "ultrarisc,dp1000-pcie"; > + reg = <0x0 0x23000000 0x0 0x01000000>, > + <0x0 0x6fff0000 0x0 0x00010000>; > + reg-names = "dbi", "config"; > + ranges = <0x81000000 0x0 0x6fbf0000 0x0 0x6fbf0000 0x0 0x00400000>, > + <0x82000000 0x0 0x60000000 0x0 0x60000000 0x0 0x0fbf0000>, > + <0xc3000000 0x80 0x00000000 0x80 0x00000000 0xd 0x00000000>; > + #address-cells = <3>; > + #size-cells = <2>; > + #interrupt-cells = <1>; > + device_type = "pci"; > + dma-coherent; > + bus-range = <0x0 0xff>; > + num-lanes = <4>; > + interrupt-parent = <&plic>; > + interrupts = <63>, <64>, <65>, <66>, <67>; > + interrupt-names = "msi", "inta", "intb", "intc", "intd"; > + interrupt-map-mask = <0x0 0x0 0x0 0x7>; > + interrupt-map = <0x0 0x0 0x0 0x1 &plic 64>, > + <0x0 0x0 0x0 0x2 &plic 65>, > + <0x0 0x0 0x0 0x3 &plic 66>, > + <0x0 0x0 0x0 0x4 &plic 67>; > + }; > + > + pcie_x4b: pcie@24000000 { > + compatible = "ultrarisc,dp1000-pcie"; > + reg = <0x0 0x24000000 0x0 0x01000000>, > + <0x0 0x7fff0000 0x0 0x00010000>; > + reg-names = "dbi", "config"; > + ranges = <0x81000000 0x0 0x7fbf0000 0x0 0x7fbf0000 0x0 0x00400000>, > + <0x82000000 0x0 0x70000000 0x0 0x70000000 0x0 0x0fbf0000>, > + <0xc3000000 0xc0 0x00000000 0xc0 0x00000000 0xd 0x00000000>; > + #address-cells = <3>; > + #size-cells = <2>; > + #interrupt-cells = <1>; > + device_type = "pci"; > + dma-coherent; > + bus-range = <0x0 0xff>; > + num-lanes = <4>; > + interrupt-parent = <&plic>; > + interrupts = <73>, <74>, <75>, <76>, <77>; > + interrupt-names = "msi", "inta", "intb", "intc", "intd"; > + interrupt-map-mask = <0x0 0x0 0x0 0x7>; > + interrupt-map = <0x0 0x0 0x0 0x1 &plic 74>, > + <0x0 0x0 0x0 0x2 &plic 75>, > + <0x0 0x0 0x0 0x3 &plic 76>, > + <0x0 0x0 0x0 0x4 &plic 77>; > + }; > + > + ethernet: ethernet@38000000 { > + compatible = "snps,dwmac", "snps,dwmac-5.10a"; > + reg = <0x00 0x38000000 0x00 0x1000000>; > + clocks = <&csr_clk>; > + clock-names = "stmmaceth"; > + interrupt-parent = <&plic>; > + interrupts = <84>; > + interrupt-names = "macirq"; > + local-mac-address = [ff ff ff ff ff ff]; Drop. Not a property of the SoC. > + max-speed = <1000>; > + phy-mode = "rgmii-id"; > + snps,txpbl = <8>; > + snps,rxpbl = <8>; I doubt that Ethernet is complete on the SoC - without MAC and all other resources. IOW, it is very weird that this is enabled here. Please explain. > + }; > + > + dmac: dma-controller@39000000 { > + compatible = "snps,axi-dma-1.01a"; > + reg = <0x0 0x39000000 0x0 0x400>; <0x0 here but why in other places is <0x00? Write consistent code. Best regards, Krzysztof _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv