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Fri, 25 Jul 2025 14:16:58 +0000 From: Matt Coster To: Krzysztof Kozlowski , Michal Wilczynski CC: Guo Ren , Fu Wei , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski , Philipp Zabel , Frank Binns , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Ulf Hansson , Marek Szyprowski , Drew Fustini , Bartosz Golaszewski , "linux-riscv@lists.infradead.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-pm@vger.kernel.org" , "dri-devel@lists.freedesktop.org" Subject: Re: [PATCH v8 2/4] dt-bindings: gpu: img,powervr-rogue: Add TH1520 GPU compatible Thread-Topic: [PATCH v8 2/4] dt-bindings: gpu: img,powervr-rogue: Add TH1520 GPU compatible Thread-Index: AQHb/W7IrTxNzJ63ZE+S8Hb10tAAhw== Date: Fri, 25 Jul 2025 14:16:58 +0000 Message-ID: <2e60530d-e214-4044-8dfc-5293832ac4fd@imgtec.com> References: <20250724-apr_14_for_sending-v8-0-0714bef83c59@samsung.com> <20250724-apr_14_for_sending-v8-2-0714bef83c59@samsung.com> <20250725-gainful-saluki-of-mathematics-3c0dd0@kuoka> <4461a785-b593-429e-b436-44cd2f1c96eb@imgtec.com> <4d79c8dd-c5fb-442c-ac65-37e7176b0cdd@linaro.org> In-Reply-To: <4d79c8dd-c5fb-442c-ac65-37e7176b0cdd@linaro.org> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: yes X-MS-TNEF-Correlator: x-ms-publictraffictype: Email x-ms-traffictypediagnostic: CWXP265MB3397:EE_|CW1P265MB7689:EE_ x-ms-office365-filtering-correlation-id: e2ef89a9-1569-4944-e998-08ddcb85eabf x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0;ARA:13230040|376014|1800799024|7416014|366016|4053099003|38070700018; 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X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: multipart/mixed; boundary="===============4859594631202459761==" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org --===============4859594631202459761== Content-Language: en-US Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="------------fTSpL7TtdmF7FYN80vuOwDhq" --------------fTSpL7TtdmF7FYN80vuOwDhq Content-Type: multipart/mixed; boundary="------------18nbOxbUWKB4bOITwWe5u0iT"; protected-headers="v1" From: Matt Coster To: Krzysztof Kozlowski , Michal Wilczynski Cc: Guo Ren , Fu Wei , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski , Philipp Zabel , Frank Binns , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Ulf Hansson , Marek Szyprowski , Drew Fustini , Bartosz Golaszewski , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, dri-devel@lists.freedesktop.org Message-ID: <2e60530d-e214-4044-8dfc-5293832ac4fd@imgtec.com> Subject: Re: [PATCH v8 2/4] dt-bindings: gpu: img,powervr-rogue: Add TH1520 GPU compatible References: <20250724-apr_14_for_sending-v8-0-0714bef83c59@samsung.com> <20250724-apr_14_for_sending-v8-2-0714bef83c59@samsung.com> <20250725-gainful-saluki-of-mathematics-3c0dd0@kuoka> <4461a785-b593-429e-b436-44cd2f1c96eb@imgtec.com> <4d79c8dd-c5fb-442c-ac65-37e7176b0cdd@linaro.org> In-Reply-To: <4d79c8dd-c5fb-442c-ac65-37e7176b0cdd@linaro.org> --------------18nbOxbUWKB4bOITwWe5u0iT Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable On 25/07/2025 12:08, Krzysztof Kozlowski wrote: > On 25/07/2025 11:00, Matt Coster wrote: >> On 25/07/2025 07:59, Krzysztof Kozlowski wrote: >>> On Thu, Jul 24, 2025 at 04:18:59PM +0200, Michal Wilczynski wrote: >>>> Update the img,powervr-rogue.yaml to include the T-HEAD TH1520 SoC's= >>>> specific GPU compatible string. >>>> >>>> The thead,th1520-gpu compatible, along with its full chain >>>> img,img-bxm-4-64, and img,img-rogue, is added to the >>>> list of recognized GPU types. >>>> >>>> While the BXM-4-64 GPU IP is designed with two distinct power domain= s, >>>> the TH1520 SoC integrates it with only a single, unified power gate = that >>>> is controllable by the kernel. >>>> >>>> To model this reality correctly while keeping the binding accurate f= or >>>> other devices, add conditional constraints to the `allOf` section: >>>> - An if block for thead,th1520-gpu enforces a maximum of one >>>> power domain and disallows the power-domain-names property. >>> >>> Why? >>> >>> This solves nothing, because you did not change the meaning of power >>> domain entry. >> >> Hi Krzysztof, >> >> Just to clarify, is this an issue that can be resolved by documenting >> the semantics of ">=3D1 power domains with names" vs "1 unnamed power >> domain" in the binding file? Or are you suggesting an alternative meth= od >> of encoding this information in devicetree? >=20 > Currently, through power-domain names, the first entry in power domains= > is the 'a' domain. We usually prefer this to be explicit - listing item= s > - but here, probably due to obviousness of names A and B, it did not ha= ppen. I'm probably being slow (it is a Friday afternoon after all), but I'm not sure I follow. For context, see my response to an earlier version of this series[1], but I'll include relevant details here. The "typical" integration of a Rogue GPU involves minimum two power domains. Annoyingly, we literally call these A, B, etc. Domain A always contains the firmware controller, which can control the gating of the other domains in hardware without getting the host OS involved. The purpose of declaring all these domains in devicetree is that they must be powered on in order (it so happens in Rogue that A->B->... is always valid so we didn't bother adding more complexity here to define the true dependencies between the domains where more than 2 are present). However, there are two exceptions to this: - The AXE-1-16M is a tiny GPU that only uses one power domain. It was also the first GPU we added support for, and as such we didn't consider the ramifications of not requiring power-domain-names in the bindings. That's the historical context for power-domain-names currently only being required for img,img-rogue compatibles, we introduced that top-level compatible as part of an overhaul to ensure we'd be able to describe all Rogue hardware more accurately. Where devicetrees containing AXE-1-16M have been updated to use the new compatible strings, they also now include power-domain-names: "a". - In a few integrations (possibly even just this one), the SoC designers chose not to take advantage of the firmware-controlled power gating and placed the entire GPU in a single power domain. The latter point is the context in which we're talking about allowing a single unnamed power domain; when we have exactly one and it covers the entire GPU. Semantically, this is subtly different from the first point. Is there any practical difference? Probably not, but devicetree is supposed to describe hardware so we may as well get pedantic. In my previous response[1], I also suggested the alternative of specifying a name for that domain (IIRC "gpu" or "top" were my original suggestions), but Michal (reasonably IMO) didn't see the point. >=20 > Disallowing power-domain names does magically change existing binding. Does this refer to the explicit power-domain-names: false? If so, is there a good/proper way to say "don't name this domain" or are we better off falling back to the alternative of giving it a generic name that we can enforce in bindings? >=20 > I think you should list the power-domains items explicitly for each > variant (see any of my other standard examples how this is done, e.g. > clock controllers). We could re-jig the bindings to do that for sure, it wouldn't change the semantics we currently have (prior to this patch). That would probably be easier to scan than the current method of having "a", "b", etc. at the top level and requiring the specific {min,max}Items by variant. [1]: https://lore.kernel.org/r/f25c1e7f-bef2-47b1-8fa8-14c9c51087a8@imgte= c.com >=20 >=20 > Best regards, > Krzysztof --=20 Matt Coster E: matt.coster@imgtec.com --------------18nbOxbUWKB4bOITwWe5u0iT-- --------------fTSpL7TtdmF7FYN80vuOwDhq Content-Type: application/pgp-signature; name="OpenPGP_signature.asc" Content-Description: OpenPGP digital signature Content-Disposition: attachment; filename="OpenPGP_signature.asc" -----BEGIN PGP SIGNATURE----- wnoEABYIACMWIQS4qDmoJvwmKhjY+nN5vBnz2d5qsAUCaIOR2gUDAAAAAAAKCRB5vBnz2d5qsEQ6 APdnj4q7AaHUMNGg2uvPGfDbl85Cv4VTz1KKr4j0iH1wAQDVNHlaClHkxLw2ui+OOS+6AlkJeafh bkLDWXIkBny6Dg== =UVUf -----END PGP SIGNATURE----- --------------fTSpL7TtdmF7FYN80vuOwDhq-- --===============4859594631202459761== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv --===============4859594631202459761==--