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Tue, 11 May 2021 12:36:09 +0000 Received: from DGGEMS401-HUB.china.huawei.com (unknown [172.30.72.59]) by szxga07-in.huawei.com (SkyGuard) with ESMTP id 4Ffclc1cMrzCr9G; Tue, 11 May 2021 20:33:16 +0800 (CST) Received: from [10.174.177.243] (10.174.177.243) by DGGEMS401-HUB.china.huawei.com (10.3.19.201) with Microsoft SMTP Server id 14.3.498.0; Tue, 11 May 2021 20:35:48 +0800 Subject: Re: [PATCH stable v5.10 0/7] arm64: Default to 32-bit wide ZONE_DMA To: Greg KH , Jing Xiangfeng CC: Nicolas Saenz Julienne , , , , , , , , , , , , , , , , , , , , , , , , , References: <20210303073319.2215839-1-jingxiangfeng@huawei.com> <9bc396116372de5b538d71d8f9ae9c3259f1002e.camel@suse.de> <827b317d7f5da6e048806922098291faacdb19f9.camel@suse.de> <604597E3.5000605@huawei.com> From: Kefeng Wang Message-ID: <31cd8432-2466-555d-7617-ae48cbcd4244@huawei.com> Date: Tue, 11 May 2021 20:35:47 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.7.0 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US X-Originating-IP: [10.174.177.243] X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210511_053608_049476_4BA7F124 X-CRM114-Status: GOOD ( 11.95 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On 2021/3/8 17:58, Greg KH wrote: > On Mon, Mar 08, 2021 at 11:20:03AM +0800, Jing Xiangfeng wrote: >> >> >> On 2021/3/7 23:24, Greg KH wrote: >>> On Thu, Mar 04, 2021 at 04:09:28PM +0100, Nicolas Saenz Julienne wrote: >>>> On Thu, 2021-03-04 at 15:17 +0100, Greg KH wrote: >>>>> On Thu, Mar 04, 2021 at 03:05:32PM +0100, Nicolas Saenz Julienne wrote: >>>>>> Hi Greg. >>>>>> >>>>>> On Thu, 2021-03-04 at 14:46 +0100, Greg KH wrote: >>>>>>> On Wed, Mar 03, 2021 at 03:33:12PM +0800, Jing Xiangfeng wrote: >>>>>>>> Using two distinct DMA zones turned out to be problematic. Here's an >>>>>>>> attempt go back to a saner default. >>>>>>> What problem does this solve? How does this fit into the stable kernel >>>>>>> rules? >>>>>> We changed the way we setup memory zones in arm64 in order to cater for >>>>>> Raspberry Pi 4's weird DMA constraints: ZONE_DMA spans the lower 1GB of memory >>>>>> and ZONE_DMA32 the rest of the 32bit address space. Since you can't allocate >>>>>> memory that crosses zone boundaries, this broke crashkernel allocations on big >>>>>> machines. This series fixes all this by parsing the HW description and checking >>>>>> for DMA constrained buses. When not found, the unnecessary zone creation is >>>>>> skipped. >>>>> What kernel/commit caused this "breakage"? >>>> 1a8e1cef7603 arm64: use both ZONE_DMA and ZONE_DMA32 >>> Thanks for the info, all now queued up. >> There is a fix in 5.11. Please consider applying the following commit to >> 5.10.y: >> >> aed5041ef9a3 of: unittest: Fix build on architectures without >> CONFIG_OF_ADDRES > > Thanks, now queued up. Hi Grep, another commit d78050ee3544 "arm64: Remove arm64_dma32_phys_limit and its uses" should be involved, thanks. "Prior to this patch, disabling CONFIG_ZONE_DMA32 leads to CMA allocation from the whole RAM as arm64_dma32_phys_limit becomes PHYS_MASK+1." from Catalin, see more from the link https://www.spinics.net/lists/arm-kernel/msg867356.html > > greg k-h > . > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv