[RFC v3 01/18] dt-bindings: clock: Add VO subsystem clock controller support

Michal Wilczynski
2025-01-20T17:23:34Z

Add a separate compatible string "thead,th1520-clk-vo" to describe the
Video Output (VO) subsystem clock controller in the T-Head TH1520 SoC.
The VO subsystem configures the clock gates for HDMI, MIPI, and GPU
components. Meanwhile, the existing AP sub-system clock controller
remains responsible for the CPU, DPU, GMAC, and TEE PLLs.

Signed-off-by: Michal Wilczynski <m.wilczynski@samsung.com>
---
.../bindings/clock/thead,th1520-clk-ap.yaml | 16 +++++++--
.../dt-bindings/clock/thead,th1520-clk-ap.h | 33 +++++++++++++++++++
2 files changed, 46 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml b/Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml
index 0129bd0ba4b3..e9ee8152ed5a 100644
--- a/Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml
+++ b/Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml
@@ -8,7 +8,8 @@ title: T-HEAD TH1520 AP sub-system clock controller

description: |
The T-HEAD TH1520 AP sub-system clock controller configures the
- CPU, DPU, GMAC and TEE PLLs.
+ CPU, DPU, GMAC and TEE PLLs. Additionally the VO subsystem configures
+ the clock gates for the HDMI, MIPI and the GPU.

SoC reference manual
https://openbeagle.org/beaglev-ahead/beaglev-ahead/-/blob/main/docs/TH1520%20System%20User%20Manual.pdf
@@ -20,14 +21,16 @@ maintainers:

properties:
compatible:
- const: thead,th1520-clk-ap
+ enum:
+ - thead,th1520-clk-ap
+ - thead,th1520-clk-vo

reg:
maxItems: 1

clocks:
items:
- - description: main oscillator (24MHz)
+ - description: main oscillator (24MHz) or CLK_VIDEO_PLL

"#clock-cells":
const: 1
@@ -51,3 +54,10 @@ examples:
clocks = <&osc>;
#clock-cells = <1>;
};
+
+ clock-controller@ff010000 {
+ compatible = "thead,th1520-clk-vo";
+ reg = <0xff010000 0x1000>;
+ clocks = <&clk CLK_VIDEO_PLL>;
+ #clock-cells = <1>;
+ };
diff --git a/include/dt-bindings/clock/thead,th1520-clk-ap.h b/include/dt-bindings/clock/thead,th1520-clk-ap.h
index a199784b3512..470fa34f9a9d 100644
--- a/include/dt-bindings/clock/thead,th1520-clk-ap.h
+++ b/include/dt-bindings/clock/thead,th1520-clk-ap.h
@@ -93,4 +93,37 @@
#define CLK_SRAM3 83
#define CLK_PLL_GMAC_100M 84
#define CLK_UART_SCLK 85
+
+/* VO clocks */
+#define CLK_AXI4_VO_ACLK 0
+#define CLK_GPU_CORE 1
+#define CLK_GPU_CFG_ACLK 2
+#define CLK_DPU_PIXELCLK0 3
+#define CLK_DPU_PIXELCLK1 4
+#define CLK_DPU_HCLK 5
+#define CLK_DPU_ACLK 6
+#define CLK_DPU_CCLK 7
+#define CLK_HDMI_SFR 8
+#define CLK_HDMI_PCLK 9
+#define CLK_HDMI_CEC 10
+#define CLK_MIPI_DSI0_PCLK 11
+#define CLK_MIPI_DSI1_PCLK 12
+#define CLK_MIPI_DSI0_CFG 13
+#define CLK_MIPI_DSI1_CFG 14
+#define CLK_MIPI_DSI0_REFCLK 15
+#define CLK_MIPI_DSI1_REFCLK 16
+#define CLK_HDMI_I2S 17
+#define CLK_X2H_DPU1_ACLK 18
+#define CLK_X2H_DPU_ACLK 19
+#define CLK_AXI4_VO_PCLK 20
+#define CLK_IOPMP_VOSYS_DPU_PCLK 21
+#define CLK_IOPMP_VOSYS_DPU1_PCLK 22
+#define CLK_IOPMP_VOSYS_GPU_PCLK 23
+#define CLK_IOPMP_DPU1_ACLK 24
+#define CLK_IOPMP_DPU_ACLK 25
+#define CLK_IOPMP_GPU_ACLK 26
+#define CLK_MIPIDSI0_PIXCLK 27
+#define CLK_MIPIDSI1_PIXCLK 28
+#define CLK_HDMI_PIXCLK 29
+
#endif
--
2.34.1