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The first part should be readable text, while the remaining parts are likely unreadable without MIME-aware tools. --8323328-1401029749-1777459124=:966 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: QUOTED-PRINTABLE On Wed, 29 Apr 2026, Jia Wang wrote: > Move the DW_UART_* register offsets and CPR bit/field definitions from > 8250_dwlib.c into 8250_dwlib.h so they can be shared by 8250_dw and > 8250_dwlib users. >=20 > Add an include guard for 8250_dwlib.h. >=20 > Signed-off-by: Jia Wang > Reviewed-by: Andy Shevchenko > --- > drivers/tty/serial/8250/8250_dw.c | 11 ------ > drivers/tty/serial/8250/8250_dwlib.c | 49 -------------------------- > drivers/tty/serial/8250/8250_dwlib.h | 67 ++++++++++++++++++++++++++++++= ++++++ > 3 files changed, 67 insertions(+), 60 deletions(-) >=20 > diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/= 8250_dw.c > index 94beadb4024d..467755bf0092 100644 > --- a/drivers/tty/serial/8250/8250_dw.c > +++ b/drivers/tty/serial/8250/8250_dw.c > @@ -34,22 +34,11 @@ > =20 > #include "8250_dwlib.h" > =20 > -/* Offsets for the DesignWare specific registers */ > -#define DW_UART_USR=090x1f /* UART Status Register */ > -#define DW_UART_DMASA=090xa8 /* DMA Software Ack */ > - > #define OCTEON_UART_USR=090x27 /* UART Status Register */ > =20 > #define RZN1_UART_TDMACR 0x10c /* DMA Control Register Transmit Mode */ > #define RZN1_UART_RDMACR 0x110 /* DMA Control Register Receive Mode */ > =20 > -/* DesignWare specific register fields */ > -#define DW_UART_IIR_IID=09=09=09GENMASK(3, 0) > - > -#define DW_UART_MCR_SIRE=09=09BIT(6) > - > -#define DW_UART_USR_BUSY=09=09BIT(0) > - > /* Renesas specific register fields */ > #define RZN1_UART_xDMACR_DMA_EN=09=09BIT(0) > #define RZN1_UART_xDMACR_1_WORD_BURST=09(0 << 1) > diff --git a/drivers/tty/serial/8250/8250_dwlib.c b/drivers/tty/serial/82= 50/8250_dwlib.c > index b055d89cfb39..8859e66d2d71 100644 > --- a/drivers/tty/serial/8250/8250_dwlib.c > +++ b/drivers/tty/serial/8250/8250_dwlib.c > @@ -13,55 +13,6 @@ > =20 > #include "8250_dwlib.h" > =20 > -/* Offsets for the DesignWare specific registers */ > -#define DW_UART_TCR=090xac /* Transceiver Control Register (RS485) */ > -#define DW_UART_DE_EN=090xb0 /* Driver Output Enable Register */ > -#define DW_UART_RE_EN=090xb4 /* Receiver Output Enable Register */ > -#define DW_UART_DLF=090xc0 /* Divisor Latch Fraction Register */ > -#define DW_UART_RAR=090xc4 /* Receive Address Register */ > -#define DW_UART_TAR=090xc8 /* Transmit Address Register */ > -#define DW_UART_LCR_EXT=090xcc /* Line Extended Control Register */ > -#define DW_UART_CPR=090xf4 /* Component Parameter Register */ > -#define DW_UART_UCV=090xf8 /* UART Component Version */ > - > -/* Receive / Transmit Address Register bits */ > -#define DW_UART_ADDR_MASK=09=09GENMASK(7, 0) > - > -/* Line Status Register bits */ > -#define DW_UART_LSR_ADDR_RCVD=09=09BIT(8) > - > -/* Transceiver Control Register bits */ > -#define DW_UART_TCR_RS485_EN=09=09BIT(0) > -#define DW_UART_TCR_RE_POL=09=09BIT(1) > -#define DW_UART_TCR_DE_POL=09=09BIT(2) > -#define DW_UART_TCR_XFER_MODE=09=09GENMASK(4, 3) > -#define DW_UART_TCR_XFER_MODE_DE_DURING_RE=09FIELD_PREP(DW_UART_TCR_XFER= _MODE, 0) > -#define DW_UART_TCR_XFER_MODE_SW_DE_OR_RE=09FIELD_PREP(DW_UART_TCR_XFER_= MODE, 1) > -#define DW_UART_TCR_XFER_MODE_DE_OR_RE=09=09FIELD_PREP(DW_UART_TCR_XFER_= MODE, 2) > - > -/* Line Extended Control Register bits */ > -#define DW_UART_LCR_EXT_DLS_E=09=09BIT(0) > -#define DW_UART_LCR_EXT_ADDR_MATCH=09BIT(1) > -#define DW_UART_LCR_EXT_SEND_ADDR=09BIT(2) > -#define DW_UART_LCR_EXT_TRANSMIT_MODE=09BIT(3) > - > -/* Component Parameter Register bits */ > -#define DW_UART_CPR_ABP_DATA_WIDTH=09GENMASK(1, 0) > -#define DW_UART_CPR_AFCE_MODE=09=09BIT(4) > -#define DW_UART_CPR_THRE_MODE=09=09BIT(5) > -#define DW_UART_CPR_SIR_MODE=09=09BIT(6) > -#define DW_UART_CPR_SIR_LP_MODE=09=09BIT(7) > -#define DW_UART_CPR_ADDITIONAL_FEATURES=09BIT(8) > -#define DW_UART_CPR_FIFO_ACCESS=09=09BIT(9) > -#define DW_UART_CPR_FIFO_STAT=09=09BIT(10) > -#define DW_UART_CPR_SHADOW=09=09BIT(11) > -#define DW_UART_CPR_ENCODED_PARMS=09BIT(12) > -#define DW_UART_CPR_DMA_EXTRA=09=09BIT(13) > -#define DW_UART_CPR_FIFO_MODE=09=09GENMASK(23, 16) > - > -/* Helper for FIFO size calculation */ > -#define DW_UART_CPR_FIFO_SIZE(a)=09(FIELD_GET(DW_UART_CPR_FIFO_MODE, (a)= ) * 16) > - > /* > * divisor =3D div(I) + div(F) > * "I" means integer, "F" means fractional > diff --git a/drivers/tty/serial/8250/8250_dwlib.h b/drivers/tty/serial/82= 50/8250_dwlib.h > index 7dd2a8e7b780..2f26f9ecacbe 100644 > --- a/drivers/tty/serial/8250/8250_dwlib.h > +++ b/drivers/tty/serial/8250/8250_dwlib.h > @@ -1,11 +1,76 @@ > /* SPDX-License-Identifier: GPL-2.0+ */ > /* Synopsys DesignWare 8250 library header file. */ > =20 > +#ifndef _SERIAL_8250_DWLIB_H_ > +#define _SERIAL_8250_DWLIB_H_ > + > +#include > +#include > #include > #include > =20 > #include "8250.h" > =20 > +/* Offsets for the DesignWare specific registers */ > +#define DW_UART_USR=090x1f /* UART Status Register */ > +#define DW_UART_DMASA=090xa8 /* DMA Software Ack */ > +#define DW_UART_TCR=090xac /* Transceiver Control Register (RS485) */ > +#define DW_UART_DE_EN=090xb0 /* Driver Output Enable Register */ > +#define DW_UART_RE_EN=090xb4 /* Receiver Output Enable Register */ > +#define DW_UART_DLF=090xc0 /* Divisor Latch Fraction Register */ > +#define DW_UART_RAR=090xc4 /* Receive Address Register */ > +#define DW_UART_TAR=090xc8 /* Transmit Address Register */ > +#define DW_UART_LCR_EXT=090xcc /* Line Extended Control Register */ > +#define DW_UART_CPR=090xf4 /* Component Parameter Register */ > +#define DW_UART_UCV=090xf8 /* UART Component Version */ > + > +/* Interrupt ID Register bits */ > +#define DW_UART_IIR_IID=09=09=09GENMASK(3, 0) > + > +/* Modem Control Register bits */ > +#define DW_UART_MCR_SIRE=09=09BIT(6) > + > +/* Line Status Register bits */ > +#define DW_UART_LSR_ADDR_RCVD=09=09BIT(8) > + > +/* UART Status Register bits */ > +#define DW_UART_USR_BUSY=09=09BIT(0) > + > +/* Transceiver Control Register bits */ > +#define DW_UART_TCR_RS485_EN=09=09BIT(0) > +#define DW_UART_TCR_RE_POL=09=09BIT(1) > +#define DW_UART_TCR_DE_POL=09=09BIT(2) > +#define DW_UART_TCR_XFER_MODE=09=09GENMASK(4, 3) > +#define DW_UART_TCR_XFER_MODE_DE_DURING_RE=09FIELD_PREP(DW_UART_TCR_XFER= _MODE, 0) > +#define DW_UART_TCR_XFER_MODE_SW_DE_OR_RE=09FIELD_PREP(DW_UART_TCR_XFER_= MODE, 1) > +#define DW_UART_TCR_XFER_MODE_DE_OR_RE=09=09FIELD_PREP(DW_UART_TCR_XFER_= MODE, 2) > + > +/* Receive / Transmit Address Register bits */ > +#define DW_UART_ADDR_MASK=09=09GENMASK(7, 0) > + > +/* Line Extended Control Register bits */ > +#define DW_UART_LCR_EXT_DLS_E=09=09BIT(0) > +#define DW_UART_LCR_EXT_ADDR_MATCH=09BIT(1) > +#define DW_UART_LCR_EXT_SEND_ADDR=09BIT(2) > +#define DW_UART_LCR_EXT_TRANSMIT_MODE=09BIT(3) > + > +/* Component Parameter Register bits */ > +#define DW_UART_CPR_ABP_DATA_WIDTH=09GENMASK(1, 0) > +#define DW_UART_CPR_AFCE_MODE=09=09BIT(4) > +#define DW_UART_CPR_THRE_MODE=09=09BIT(5) > +#define DW_UART_CPR_SIR_MODE=09=09BIT(6) > +#define DW_UART_CPR_SIR_LP_MODE=09=09BIT(7) > +#define DW_UART_CPR_ADDITIONAL_FEATURES=09BIT(8) > +#define DW_UART_CPR_FIFO_ACCESS=09=09BIT(9) > +#define DW_UART_CPR_FIFO_STAT=09=09BIT(10) > +#define DW_UART_CPR_SHADOW=09=09BIT(11) > +#define DW_UART_CPR_ENCODED_PARMS=09BIT(12) > +#define DW_UART_CPR_DMA_EXTRA=09=09BIT(13) > +#define DW_UART_CPR_FIFO_MODE=09=09GENMASK(23, 16) > + > +/* Helper for FIFO size calculation */ > +#define DW_UART_CPR_FIFO_SIZE(a)=09(FIELD_GET(DW_UART_CPR_FIFO_MODE, (a)= ) * 16) > + > struct dw8250_port_data { > =09/* Port properties */ > =09int=09=09=09line; > @@ -38,3 +103,5 @@ static inline void dw8250_writel_ext(struct uart_port = *p, int offset, u32 reg) > =09else > =09=09writel(reg, p->membase + offset); > } > + > +#endif /* _SERIAL_8250_DWLIB_H_ */ Reviewed-by: Ilpo J=C3=A4rvinen --=20 i. --8323328-1401029749-1777459124=:966 Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv --8323328-1401029749-1777459124=:966--