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From: William Qiu <william.qiu@starfivetech.com>
To: Conor Dooley <conor@kernel.org>
Cc: <devicetree@vger.kernel.org>, <linux-spi@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>, <linux-riscv@lists.infradead.org>,
	Mark Brown <broonie@kernel.org>, Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Conor Dooley <conor+dt@kernel.org>,
	"Emil Renner Berthing" <kernel@esmil.dk>,
	Ziv Xu <ziv.xu@starfivetech.com>
Subject: Re: [PATCH v2 1/3] dt-bindings: qspi: cdns,qspi-nor: Add clocks for StarFive JH7110 SoC
Date: Tue, 6 Jun 2023 11:34:14 +0800	[thread overview]
Message-ID: <39ff6f3f-4713-3864-4325-3dbde811a220@starfivetech.com> (raw)
In-Reply-To: <20230602-impurity-broker-28cc27869b64@spud>



On 2023/6/3 2:02, Conor Dooley wrote:
> On Fri, Jun 02, 2023 at 04:49:23PM +0800, William Qiu wrote:
>> The QSPI controller needs three clock items to work properly on StarFive
>> JH7110 SoC, so there is need to change the maxItems's value to 3. Other
>> platforms do not have this constraint.
>> 
>> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
>> Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
>> ---
>>  .../devicetree/bindings/spi/cdns,qspi-nor.yaml    | 15 ++++++++++++---
>>  1 file changed, 12 insertions(+), 3 deletions(-)
>> 
>> diff --git a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml
>> index b310069762dd..b6a27171d965 100644
>> --- a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml
>> +++ b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml
>> @@ -26,6 +26,15 @@ allOf:
>>              const: starfive,jh7110-qspi
>>      then:
>>        properties:
>> +        clocks:
>> +          maxItems: 3
>> +
>> +        clock-names:
>> +          items:
>> +            - const: ref_clk
> 
> Aww, I liked Mark's suggestions better.
> If you are respinning to fix the LKP reported issue w/ ignoring the result
> of enabling the clocks, could you chop the _clk off of this one?
> 
> Otherwise,
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> 
> Thanks,
> Conor.

Hi Conor,

Thanks for taking time to review this patch series.
About the clock name, I would take Mark's suggestions, and will update it in
next version.

Best regards,
William

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  reply	other threads:[~2023-06-06  3:34 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-06-02  8:49 [PATCH v2 0/3] Add initialization of clock for StarFive JH7110 SoC William Qiu
2023-06-02  8:49 ` [PATCH v2 1/3] dt-bindings: qspi: cdns,qspi-nor: Add clocks " William Qiu
2023-06-02 18:02   ` Conor Dooley
2023-06-06  3:34     ` William Qiu [this message]
2023-06-06 12:43   ` Krzysztof Kozlowski
2023-06-19  7:27     ` William Qiu
2023-06-02  8:49 ` [PATCH v2 2/3] spi: cadence-quadspi: Add clock configuration for StarFive JH7110 QSPI William Qiu
2023-06-02 12:33   ` kernel test robot
2023-06-06  3:32     ` William Qiu
2023-06-02  8:49 ` [PATCH v2 3/3] riscv: dts: starfive: Add QSPI controller node for StarFive JH7110 SoC William Qiu
2023-08-04 19:04 ` (subset) [PATCH v2 0/3] Add initialization of clock " Mark Brown

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