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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On 30.08.2022 15:52, Conor Dooley wrote: > The id and offset are the only thing differentiating the clock structs > from "regular" clock structures. On the pretext of converting to more > normal structures, move the id and offset out of the clock structs and > into the hw structs instead. > > Reviewed-by: Daire McNamara > Signed-off-by: Conor Dooley Reviewed-by: Claudiu Beznea > --- > drivers/clk/microchip/clk-mpfs.c | 30 +++++++++++++++--------------- > 1 file changed, 15 insertions(+), 15 deletions(-) > > diff --git a/drivers/clk/microchip/clk-mpfs.c b/drivers/clk/microchip/clk-mpfs.c > index 008b76d81485..845658751690 100644 > --- a/drivers/clk/microchip/clk-mpfs.c > +++ b/drivers/clk/microchip/clk-mpfs.c > @@ -53,8 +53,6 @@ struct mpfs_msspll_hw_clock { > > struct mpfs_cfg_clock { > const struct clk_div_table *table; > - unsigned int id; > - u32 reg_offset; > u8 shift; > u8 width; > u8 flags; > @@ -65,12 +63,13 @@ struct mpfs_cfg_hw_clock { > void __iomem *sys_base; > struct clk_hw hw; > struct clk_init_data init; > + unsigned int id; > + u32 reg_offset; > }; > > #define to_mpfs_cfg_clk(_hw) container_of(_hw, struct mpfs_cfg_hw_clock, hw) > > struct mpfs_periph_clock { > - unsigned int id; > u8 shift; > }; > > @@ -78,6 +77,7 @@ struct mpfs_periph_hw_clock { > struct mpfs_periph_clock periph; > void __iomem *sys_base; > struct clk_hw hw; > + unsigned int id; > }; > > #define to_mpfs_periph_clk(_hw) container_of(_hw, struct mpfs_periph_hw_clock, hw) > @@ -243,7 +243,7 @@ static unsigned long mpfs_cfg_clk_recalc_rate(struct clk_hw *hw, unsigned long p > void __iomem *base_addr = cfg_hw->sys_base; > u32 val; > > - val = readl_relaxed(base_addr + cfg->reg_offset) >> cfg->shift; > + val = readl_relaxed(base_addr + cfg_hw->reg_offset) >> cfg->shift; > val &= clk_div_mask(cfg->width); > > return divider_recalc_rate(hw, prate, val, cfg->table, cfg->flags, cfg->width); > @@ -272,10 +272,10 @@ static int mpfs_cfg_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned > return divider_setting; > > spin_lock_irqsave(&mpfs_clk_lock, flags); > - val = readl_relaxed(base_addr + cfg->reg_offset); > + val = readl_relaxed(base_addr + cfg_hw->reg_offset); > val &= ~(clk_div_mask(cfg->width) << cfg_hw->cfg.shift); > val |= divider_setting << cfg->shift; > - writel_relaxed(val, base_addr + cfg->reg_offset); > + writel_relaxed(val, base_addr + cfg_hw->reg_offset); > > spin_unlock_irqrestore(&mpfs_clk_lock, flags); > > @@ -289,11 +289,11 @@ static const struct clk_ops mpfs_clk_cfg_ops = { > }; > > #define CLK_CFG(_id, _name, _parent, _shift, _width, _table, _flags, _offset) { \ > - .cfg.id = _id, \ > + .id = _id, \ > .cfg.shift = _shift, \ > .cfg.width = _width, \ > .cfg.table = _table, \ > - .cfg.reg_offset = _offset, \ > + .reg_offset = _offset, \ > .cfg.flags = _flags, \ > .hw.init = CLK_HW_INIT(_name, _parent, &mpfs_clk_cfg_ops, 0), \ > } > @@ -306,11 +306,11 @@ static struct mpfs_cfg_hw_clock mpfs_cfg_clks[] = { > CLK_CFG(CLK_AHB, "clk_ahb", "clk_msspll", 4, 2, mpfs_div_ahb_table, 0, > REG_CLOCK_CONFIG_CR), > { > - .cfg.id = CLK_RTCREF, > + .id = CLK_RTCREF, > .cfg.shift = 0, > .cfg.width = 12, > .cfg.table = mpfs_div_rtcref_table, > - .cfg.reg_offset = REG_RTC_CLOCK_CR, > + .reg_offset = REG_RTC_CLOCK_CR, > .cfg.flags = CLK_DIVIDER_ONE_BASED, > .hw.init = > CLK_HW_INIT_PARENTS_DATA("clk_rtcref", mpfs_ext_ref, &mpfs_clk_cfg_ops, 0), > @@ -338,9 +338,9 @@ static int mpfs_clk_register_cfgs(struct device *dev, struct mpfs_cfg_hw_clock * > ret = mpfs_clk_register_cfg(dev, cfg_hw, sys_base); > if (ret) > return dev_err_probe(dev, ret, "failed to register clock id: %d\n", > - cfg_hw->cfg.id); > + cfg_hw->id); > > - id = cfg_hw->cfg.id; > + id = cfg_hw->id; > data->hw_data.hws[id] = &cfg_hw->hw; > } > > @@ -408,7 +408,7 @@ static const struct clk_ops mpfs_periph_clk_ops = { > }; > > #define CLK_PERIPH(_id, _name, _parent, _shift, _flags) { \ > - .periph.id = _id, \ > + .id = _id, \ > .periph.shift = _shift, \ > .hw.init = CLK_HW_INIT_HW(_name, _parent, &mpfs_periph_clk_ops, \ > _flags), \ > @@ -482,9 +482,9 @@ static int mpfs_clk_register_periphs(struct device *dev, struct mpfs_periph_hw_c > ret = mpfs_clk_register_periph(dev, periph_hw, sys_base); > if (ret) > return dev_err_probe(dev, ret, "failed to register clock id: %d\n", > - periph_hw->periph.id); > + periph_hw->id); > > - id = periph_hws[i].periph.id; > + id = periph_hws[i].id; > data->hw_data.hws[id] = &periph_hw->hw; > } > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv