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Mon, 01 Jun 2020 10:45:05 +0100 MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII; format=flowed Content-Transfer-Encoding: 7bit Date: Mon, 01 Jun 2020 10:45:05 +0100 From: Marc Zyngier To: Anup Patel Subject: Re: [PATCH v7 3/6] irqchip: RISC-V per-HART local interrupt controller driver In-Reply-To: <20200601091543.943678-4-anup.patel@wdc.com> References: <20200601091543.943678-1-anup.patel@wdc.com> <20200601091543.943678-4-anup.patel@wdc.com> User-Agent: Roundcube Webmail/1.4.4 Message-ID: <43c4770a9c8a2e03242a5176037f823c@kernel.org> X-Sender: maz@kernel.org X-SA-Exim-Connect-IP: 51.254.78.96 X-SA-Exim-Rcpt-To: anup.patel@wdc.com, palmer@dabbelt.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu, daniel.lezcano@linaro.org, tglx@linutronix.de, jason@lakedaemon.net, atish.patra@wdc.com, Alistair.Francis@wdc.com, anup@brainfault.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, palmerdabbelt@google.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200601_024513_672466_FE051733 X-CRM114-Status: GOOD ( 10.89 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Albert Ou , Jason Cooper , Anup Patel , Daniel Lezcano , linux-kernel@vger.kernel.org, Atish Patra , Palmer Dabbelt , Paul Walmsley , Palmer Dabbelt , Alistair Francis , Thomas Gleixner , linux-riscv@lists.infradead.org Sender: "linux-riscv" Errors-To: linux-riscv-bounces+infradead-linux-riscv=archiver.kernel.org@lists.infradead.org On 2020-06-01 10:15, Anup Patel wrote: > The RISC-V per-HART local interrupt controller manages software > interrupts, timer interrupts, external interrupts (which are routed > via the platform level interrupt controller) and other per-HART > local interrupts. > > We add a driver for the RISC-V local interrupt controller, which > eventually replaces the RISC-V architecture code, allowing for a > better split between arch code and drivers. > > The driver is compliant with RISC-V Hart-Level Interrupt Controller > DT bindings located at: > Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.txt > > Co-developed-by: Palmer Dabbelt > Signed-off-by: Palmer Dabbelt > Signed-off-by: Anup Patel > Acked-by: Palmer Dabbelt > --- > arch/riscv/Kconfig | 1 + > arch/riscv/include/asm/irq.h | 2 - > arch/riscv/kernel/irq.c | 33 +------ > arch/riscv/kernel/traps.c | 2 - > drivers/irqchip/Kconfig | 13 +++ > drivers/irqchip/Makefile | 1 + > drivers/irqchip/irq-riscv-intc.c | 146 ++++++++++++++++++++++++++++++ > drivers/irqchip/irq-sifive-plic.c | 30 ++++-- > include/linux/cpuhotplug.h | 1 + > 9 files changed, 188 insertions(+), 41 deletions(-) > create mode 100644 drivers/irqchip/irq-riscv-intc.c Reviewed-by: Marc Zyngier M. -- Jazz is not dead. It just smells funny...