[PATCH v5 09/10] riscv: microchip: icicle: readability fixes

Conor Dooley
2022-05-09T14:27:36Z

Fix the sort order of the status properties, remove some
extra whitespace in the mmc entry & add whitespace to the mac entry
containing the phys so that the dt is easier to read.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
index 739dfa52bed1..9cd1a30edf2c 100644
--- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
+++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
@@ -64,8 +64,6 @@ &mmuart4 {
};

&mmc {
- status = "okay";
-
bus-width = <4>;
disable-wp;
cap-sd-highspeed;
@@ -77,6 +75,7 @@ &mmc {
sd-uhs-sdr25;
sd-uhs-sdr50;
sd-uhs-sdr104;
+ status = "okay";
};

&spi0 {
@@ -106,16 +105,19 @@ &i2c2 {
&mac0 {
phy-mode = "sgmii";
phy-handle = <&phy0>;
+ status = "okay";
};

&mac1 {
- status = "okay";
phy-mode = "sgmii";
phy-handle = <&phy1>;
+ status = "okay";
+
phy1: ethernet-phy@9 {
reg = <9>;
ti,fifo-depth = <0x1>;
};
+
phy0: ethernet-phy@8 {
reg = <8>;
ti,fifo-depth = <0x1>;