[PATCH v5 10/10] riscv: dts: icicle: sort nodes alphabetically

Conor Dooley
2022-05-09T14:27:33Z

The icicle device tree is in a "random" order, so clean it up and sort
its elements alphabetically to match the newly added PolarBerry dts.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
.../boot/dts/microchip/mpfs-icicle-kit.dts | 104 +++++++++---------
1 file changed, 52 insertions(+), 52 deletions(-)

diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
index 9cd1a30edf2c..044982a11df5 100644
--- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
+++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
@@ -43,23 +43,57 @@ ddrc_cache_hi: memory@1000000000 {
};
};

-&refclk {
- clock-frequency = <125000000>;
+&core_pwm0 {
+ status = "okay";
};

-&mmuart1 {
+&gpio2 {
+ interrupts = <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>;
status = "okay";
};

-&mmuart2 {
+&i2c0 {
status = "okay";
};

-&mmuart3 {
+&i2c1 {
status = "okay";
};

-&mmuart4 {
+&i2c2 {
+ status = "okay";
+};
+
+&mac0 {
+ phy-mode = "sgmii";
+ phy-handle = <&phy0>;
+ status = "okay";
+};
+
+&mac1 {
+ phy-mode = "sgmii";
+ phy-handle = <&phy1>;
+ status = "okay";
+
+ phy1: ethernet-phy@9 {
+ reg = <9>;
+ ti,fifo-depth = <0x1>;
+ };
+
+ phy0: ethernet-phy@8 {
+ reg = <8>;
+ ti,fifo-depth = <0x1>;
+ };
+};
+
+&mbox {
status = "okay";
};

@@ -78,74 +112,43 @@ &mmc {
status = "okay";
};

-&spi0 {
- status = "okay";
-};
-
-&spi1 {
- status = "okay";
-};
-
-&qspi {
+&mmuart1 {
status = "okay";
};

-&i2c0 {
+&mmuart2 {
status = "okay";
};

-&i2c1 {
+&mmuart3 {
status = "okay";
};

-&i2c2 {
+&mmuart4 {
status = "okay";
};

-&mac0 {
- phy-mode = "sgmii";
- phy-handle = <&phy0>;
+&pcie {
status = "okay";
};

-&mac1 {
- phy-mode = "sgmii";
- phy-handle = <&phy1>;
+&qspi {
status = "okay";
-
- phy1: ethernet-phy@9 {
- reg = <9>;
- ti,fifo-depth = <0x1>;
- };
-
- phy0: ethernet-phy@8 {
- reg = <8>;
- ti,fifo-depth = <0x1>;
- };
};

-&gpio2 {
- interrupts = <53>, <53>, <53>, <53>,
- <53>, <53>, <53>, <53>,
- <53>, <53>, <53>, <53>,
- <53>, <53>, <53>, <53>,
- <53>, <53>, <53>, <53>,
- <53>, <53>, <53>, <53>,
- <53>, <53>, <53>, <53>,
- <53>, <53>, <53>, <53>;
- status = "okay";
+&refclk {
+ clock-frequency = <125000000>;
};

&rtc {
status = "okay";
};

-&usb {
+&spi0 {
status = "okay";
- dr_mode = "host";
};

-&mbox {
+&spi1 {
status = "okay";
};

@@ -153,10 +156,7 @@ &syscontroller {
status = "okay";
};

-&pcie {
- status = "okay";
-};
-
-&core_pwm0 {
+&usb {
status = "okay";
+ dr_mode = "host";
};