From: Ben Dooks <ben.dooks@codethink.co.uk>
To: linux-riscv@lists.infradead.org
Subject: Re: [PATCH 3/3] riscv: add trap and emulation for RDCYCLE
Date: Tue, 17 Sep 2024 15:08:57 +0100 [thread overview]
Message-ID: <44dfbf73-a6af-490e-b1cb-182583d5e7f5@codethink.co.uk> (raw)
In-Reply-To: <20240917130853.18657-4-ben.dooks@codethink.co.uk>
On 17/09/2024 14:08, Ben Dooks wrote:
> Add a trap for RDCYCLE and emulate it as RDTIME instruciton.
>
> This is an initial PoC and should probably be made more generic
> way of trapping and dealing with bad instructions
>
> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
> ---
> arch/riscv/kernel/traps.c | 31 +++++++++++++++++++++++++++++++
> 1 file changed, 31 insertions(+)
>
> diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c
> index 1c3fab272fd1..51ea28ebf54d 100644
> --- a/arch/riscv/kernel/traps.c
> +++ b/arch/riscv/kernel/traps.c
> @@ -167,6 +167,35 @@ DO_ERROR_INFO(do_trap_insn_misaligned,
> DO_ERROR_INFO(do_trap_insn_fault,
> SIGSEGV, SEGV_ACCERR, "instruction access fault");
>
> +#define is_system(__i) (((__i) & 0x7f) == RVG_OPCODE_SYSTEM)
> +
> +static bool riscv_try_csr_fixup_user(struct pt_regs *regs, u32 insn)
> +{
> + /* expecting a 4 byte CSR instruction (*/
> + if (unlikely(GET_INSN_LENGTH(insn) != 4))
> + return false;
> +
> + if (is_system(insn)) {
> + u32 csr = insn >> RVG_SYSTEM_CSR_OFF;
> + u32 rd = (insn >> RVG_RD_OPOFF) & RVG_RD_MASK;
> + u32 rs = (insn >> RVG_RS1_OPOFF) & RVG_RS1_MASK;
> + u32 funct3 = (insn >> RV_INSN_FUNCT3_OPOFF) & 0x7;
> +
> + if (rs == 0 && funct3 == 2 && csr == CSR_CYCLE) {
> + u64 val = csr_read(CSR_TIME);
> + /* we've got a RDCCLYE, emulated it with CSR_TIME */
> +
> + printk_ratelimited("PID %d: process using RDCYCLE, emulating with RDTIME\n", current->pid);
> +
> + regs_set_register(regs, rd*sizeof(unsigned long), val);
> + regs->epc += 4;
> + return true;
> + }
> + }
> +
> + return false;
> +}
> +
> asmlinkage __visible __trap_section void do_trap_insn_illegal(struct pt_regs *regs)
> {
> bool handled;
> @@ -186,6 +215,8 @@ asmlinkage __visible __trap_section void do_trap_insn_illegal(struct pt_regs *re
> }
>
> handled = riscv_v_first_use_handler(regs, insn);
> + if (!handle)
> + handled = riscv_try_csr_fixup_user(regs, insn);
>
> local_irq_disable();
>
oops, forgot to fold in a fix patch, this has 2 issues.
--
Ben Dooks http://www.codethink.co.uk/
Senior Engineer Codethink - Providing Genius
https://www.codethink.co.uk/privacy.html
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next prev parent reply other threads:[~2024-09-17 16:15 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-09-17 13:08 RFC: extern illegal instruction trap and trap RDCYCLE Ben Dooks
2024-09-17 13:08 ` [PATCH 1/3] riscv: ptrace: add regs_set_register() Ben Dooks
2024-09-17 13:08 ` [PATCH 2/3] riscv: traps: make insn fetch common in unknown instruction Ben Dooks
2024-09-17 13:08 ` [PATCH 3/3] riscv: add trap and emulation for RDCYCLE Ben Dooks
2024-09-17 14:08 ` Ben Dooks [this message]
2024-09-18 6:45 ` Andrew Jones
2024-09-18 9:07 ` Ben Dooks
2024-09-18 9:15 ` Ben Dooks
2024-09-17 13:46 ` RFC: extern illegal instruction trap and trap RDCYCLE Palmer Dabbelt
2024-09-17 14:01 ` Ben Dooks
2024-09-18 9:55 ` Atish Patra
2024-09-18 9:57 ` Ben Dooks
2024-09-18 23:23 ` Atish Kumar Patra
2024-10-01 9:41 ` Alexandre Ghiti
2024-10-01 21:00 ` Ben Dooks
2024-10-01 21:07 ` Ben Dooks
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