From: <Conor.Dooley@microchip.com>
To: <mturquette@baylibre.com>, <sboyd@kernel.org>,
<robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>,
<palmer@dabbelt.com>, <Daire.McNamara@microchip.com>,
<Hugh.Breslin@microchip.com>
Cc: <paul.walmsley@sifive.com>, <aou@eecs.berkeley.edu>,
<linux-clk@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <linux-riscv@lists.infradead.org>
Subject: Re: [PATCH v2 2/6] dt-bindings: clk: document PolarFire SoC fabric clocks
Date: Mon, 22 Aug 2022 11:53:07 +0000 [thread overview]
Message-ID: <470d663f-7150-1df9-9ce0-93087feb7819@microchip.com> (raw)
In-Reply-To: <20220822112928.2727437-3-conor.dooley@microchip.com>
On 22/08/2022 12:29, Conor Dooley wrote:
> On PolarFire SoC there are 4 PLL/DLL blocks, located in each of the
> ordinal corners of the chip, which our documentation refers to as
> "Clock Conditioning Circuitry". PolarFire SoC is an FPGA, these are
> highly configurable & many of the input clocks are optional.
>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> + clock-names:
> + minItems: 2
> + items:
> + - const: pll0_ref0
> + - const: pll0_ref1
> + - const: pll1_ref0
> + - const: pll1_ref1
> + - const: dll0_ref
> + - const: dll1_ref
> +
> + '#clock-cells':
> + const: 1
> + description: |
> + The clock consumer should specify the desired clock by having the clock
> + ID in its "clocks" phandle cell.
> + See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list of
> + PolarFire clock IDs.
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> + - clock-output-names
Meh, didn't notice I had left this here.. Must've crept back in while
I was rebasing my v2 changes.
Either way Kryzysztof, I settled on removing the ordinal based naming
entirely. I could not get trying the ordinal names & then falling back
cleanly enough for my liking, so I dropped the whole thing.
> + - '#clock-cells'
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + clock-controller@38100000 {
> + compatible = "microchip,mpfs-ccc";
> + reg = <0x38010000 0x1000>, <0x38020000 0x1000>,
> + <0x39010000 0x1000>, <0x39020000 0x1000>;
> + #clock-cells = <1>;
> + clocks = <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>,
> + <&refclk_ccc>, <&refclk_ccc>;
> + clock-names = "pll0_ref0", "pll0_ref1", "pll1_ref0", "pll1_ref1",
> + "dll0_ref", "dll1_ref";
> + };
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next prev parent reply other threads:[~2022-08-22 11:53 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-22 11:29 [PATCH v2 0/6] Add PolarFire SoC Fabric Clock Conditioning Circuitry Support Conor Dooley
2022-08-22 11:29 ` [PATCH v2 1/6] dt-bindings: clk: rename mpfs-clkcfg binding Conor Dooley
2022-08-22 11:29 ` [PATCH v2 2/6] dt-bindings: clk: document PolarFire SoC fabric clocks Conor Dooley
2022-08-22 11:53 ` Conor.Dooley [this message]
2022-08-22 19:40 ` Rob Herring
2022-08-22 19:44 ` Conor.Dooley
2022-08-22 21:53 ` Rob Herring
2022-08-22 11:29 ` [PATCH v2 3/6] dt-bindings: clk: add PolarFire SoC fabric clock ids Conor Dooley
2022-08-22 11:29 ` [PATCH v2 4/6] clk: microchip: add PolarFire SoC fabric clock support Conor Dooley
2022-08-22 11:29 ` [PATCH v2 5/6] dt-bindings: riscv: microchip: document icicle reference design Conor Dooley
2022-08-22 11:29 ` [PATCH v2 6/6] riscv: dts: microchip: add the mpfs' fabric clock control Conor Dooley
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