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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Tue, Dec 23, 2025 at 01:03:27PM +0000, Yao Zi wrote: > On Tue, Dec 23, 2025 at 05:50:08PM +0800, Troy Mitchell wrote: > > On Tue, Dec 23, 2025 at 05:42:26PM +0800, Inochi Amaoto wrote: > > > On Tue, Dec 23, 2025 at 05:11:12PM +0800, Troy Mitchell wrote: > > > > IO domain power control registers are used to configure the operating > > > > voltage of dual-voltage GPIO banks. By default, these registers are > > > > configured for 3.3V operation. As a result, even when a GPIO bank is > > > > externally supplied with 1.8V, the internal logic continues to > > > > operate in the 3.3V domain, which may lead to functional failures. > > > > > > > > This patch adds support for programming the IO domain power control > > > > registers, allowing dual-voltage GPIO banks to be explicitly configured > > > > for 1.8V operation when required. > > > > > > > > Care must be taken when configuring these registers. If a GPIO bank is > > > > externally supplied with 3.3V while the corresponding IO power domain > > > > is configured for 1.8V, external current injection (back-powering) > > > > may occur, potentially causing damage to the GPIO pin. > > > > > > > > Due to these hardware constraints and safety considerations, the IO > > > > domain power control registers are implemented as secure registers. > > > > Access to these registers requires unlocking via the AIB Secure Access > > > > Register (ASAR) in the APBC block before a single read or write > > > > operation can be performed. > > > > > > > > Signed-off-by: Troy Mitchell > > > > --- > > > > arch/riscv/boot/dts/spacemit/k1.dtsi | 4 +- > > > > drivers/pinctrl/spacemit/pinctrl-k1.c | 131 +++++++++++++++++++++++++++++++++- > > > > 2 files changed, 131 insertions(+), 4 deletions(-) > > > > > > > > > > > diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi > > > > index 7818ca4979b6a7755722919a5958512aa11950ab..23ecb19624f227f3c39de35bf3078379f7a2490e 100644 > > > > --- a/arch/riscv/boot/dts/spacemit/k1.dtsi > > > > +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi > > > > @@ -565,10 +565,12 @@ i2c8: i2c@d401d800 { > > > > > > > > pinctrl: pinctrl@d401e000 { > > > > compatible = "spacemit,k1-pinctrl"; > > > > - reg = <0x0 0xd401e000 0x0 0x400>; > > > > + reg = <0x0 0xd401e000 0x0 0x400>, > > > > + <0x0 0xd401e800 0x0 0x34>; > > > > clocks = <&syscon_apbc CLK_AIB>, > > > > <&syscon_apbc CLK_AIB_BUS>; > > > > clock-names = "func", "bus"; > > > > + spacemit,apbc = <&syscon_apbc 0x50>; > > > > }; > > > > > > If you insist on a new reg field, you should change the binding as well. > > Yes, I forgot to modify the binding. > > This will also break ABI compatibility with older devicetrees, I > strongly suggest against a new item in reg property. > > Furthermore, it's unreasonable to describe d401_e000 - d401_e400 and > d401_e800 - d401_e834 as separate memory regions. TRM claims the region > starting from 0xd401_e000 with length 0xc00 is "Pad Configuration". So I > think this separation neither simplifies anything nor matches the > hardware. > > > > This change breaks binding, can we use something like <0x0 0xd401e000 0x0 0x1000>? > > If the TRM is correct, we probably can and should. I have double checked. Inochi is correct. I'll fix it in the next version. Thanks! - Troy _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv