From: "Heiko Stübner" <heiko@sntech.de>
To: linux-riscv@lists.infradead.org, Andrew Jones <ajones@ventanamicro.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Conor Dooley <conor.dooley@microchip.com>,
Anup Patel <apatel@ventanamicro.com>,
Atish Patra <atishp@rivosinc.com>
Subject: Re: [PATCH v2 1/3] RISC-V: Improve use of isa2hwcap[]
Date: Thu, 27 Oct 2022 15:05:46 +0200 [thread overview]
Message-ID: <4911272.GXAFRqVoOG@diego> (raw)
In-Reply-To: <20221024091309.406906-2-ajones@ventanamicro.com>
Am Montag, 24. Oktober 2022, 11:13:07 CEST schrieb Andrew Jones:
> Improve isa2hwcap[] by removing it from static storage, as
> riscv_fill_hwcap() is only called once, and by reducing its size
> from 256 bytes to 26. The latter improvement is possible because
> isa2hwcap[] will never be indexed with capital letters and we can
> precompute the offsets from 'a'.
>
> No functional change intended.
>
> Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
> ---
> arch/riscv/kernel/cpufeature.c | 20 +++++++++++---------
> 1 file changed, 11 insertions(+), 9 deletions(-)
>
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index 694267d1fe81..4677320d7e31 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -74,15 +74,15 @@ void __init riscv_fill_hwcap(void)
> const char *isa;
> char print_str[NUM_ALPHA_EXTS + 1];
> int i, j, rc;
> - static unsigned long isa2hwcap[256] = {0};
> + unsigned long isa2hwcap[26] = {0};
> unsigned long hartid;
>
> - isa2hwcap['i'] = isa2hwcap['I'] = COMPAT_HWCAP_ISA_I;
> - isa2hwcap['m'] = isa2hwcap['M'] = COMPAT_HWCAP_ISA_M;
> - isa2hwcap['a'] = isa2hwcap['A'] = COMPAT_HWCAP_ISA_A;
> - isa2hwcap['f'] = isa2hwcap['F'] = COMPAT_HWCAP_ISA_F;
> - isa2hwcap['d'] = isa2hwcap['D'] = COMPAT_HWCAP_ISA_D;
> - isa2hwcap['c'] = isa2hwcap['C'] = COMPAT_HWCAP_ISA_C;
> + isa2hwcap['i' - 'a'] = COMPAT_HWCAP_ISA_I;
> + isa2hwcap['m' - 'a'] = COMPAT_HWCAP_ISA_M;
> + isa2hwcap['a' - 'a'] = COMPAT_HWCAP_ISA_A;
> + isa2hwcap['f' - 'a'] = COMPAT_HWCAP_ISA_F;
> + isa2hwcap['d' - 'a'] = COMPAT_HWCAP_ISA_D;
> + isa2hwcap['c' - 'a'] = COMPAT_HWCAP_ISA_C;
>
> elf_hwcap = 0;
>
> @@ -196,8 +196,10 @@ void __init riscv_fill_hwcap(void)
> if (unlikely(ext_err))
> continue;
> if (!ext_long) {
> - this_hwcap |= isa2hwcap[(unsigned char)(*ext)];
> - set_bit(*ext - 'a', this_isa);
> + int nr = *ext - 'a';
> +
> + this_hwcap |= isa2hwcap[nr];
> + set_bit(nr, this_isa);
> } else {
> SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF);
> SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT);
>
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next prev parent reply other threads:[~2022-10-27 13:07 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-24 9:13 [PATCH v2 0/3] RISC-V: Ensure Zicbom has a valid block size Andrew Jones
2022-10-24 9:13 ` [PATCH v2 1/3] RISC-V: Improve use of isa2hwcap[] Andrew Jones
2022-10-27 13:05 ` Heiko Stübner [this message]
2022-10-24 9:13 ` [PATCH v2 2/3] RISC-V: Introduce riscv_isa_extension_check Andrew Jones
2022-10-27 13:08 ` Heiko Stübner
2022-10-24 9:13 ` [PATCH v2 3/3] RISC-V: Ensure Zicbom has a valid block size Andrew Jones
2022-10-24 9:33 ` Conor Dooley
2022-10-27 13:16 ` Heiko Stübner
2022-10-27 14:16 ` Andrew Jones
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