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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Tue, Dec 23, 2025 at 05:32:28PM +0800, Yixun Lan wrote: > Hi Troy, > > On 17:11 Tue 23 Dec , Troy Mitchell wrote: > > IO domain power control registers are used to configure the operating > > voltage of dual-voltage GPIO banks. By default, these registers are > > configured for 3.3V operation. As a result, even when a GPIO bank is > > externally supplied with 1.8V, the internal logic continues to > > operate in the 3.3V domain, which may lead to functional failures. > > > > This patch adds support for programming the IO domain power control > > registers, allowing dual-voltage GPIO banks to be explicitly configured > > for 1.8V operation when required. > > > > Care must be taken when configuring these registers. If a GPIO bank is > > externally supplied with 3.3V while the corresponding IO power domain > > is configured for 1.8V, external current injection (back-powering) > > may occur, potentially causing damage to the GPIO pin. > > > > Due to these hardware constraints and safety considerations, the IO > > domain power control registers are implemented as secure registers. > > Access to these registers requires unlocking via the AIB Secure Access > > Register (ASAR) in the APBC block before a single read or write > > operation can be performed. > > > > Signed-off-by: Troy Mitchell > > --- > > arch/riscv/boot/dts/spacemit/k1.dtsi | 4 +- > > drivers/pinctrl/spacemit/pinctrl-k1.c | 131 +++++++++++++++++++++++++++++++++- > > 2 files changed, 131 insertions(+), 4 deletions(-) > > > > diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi > > index 7818ca4979b6a7755722919a5958512aa11950ab..23ecb19624f227f3c39de35bf3078379f7a2490e 100644 > > --- a/arch/riscv/boot/dts/spacemit/k1.dtsi > > +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi > dtsi should go as separated patch, then route to SoC tree OH I forgot that. Thanks. > > > @@ -565,10 +565,12 @@ i2c8: i2c@d401d800 { > > > > pinctrl: pinctrl@d401e000 { > > compatible = "spacemit,k1-pinctrl"; > > - reg = <0x0 0xd401e000 0x0 0x400>; > > + reg = <0x0 0xd401e000 0x0 0x400>, > > + <0x0 0xd401e800 0x0 0x34>; > > clocks = <&syscon_apbc CLK_AIB>, > > <&syscon_apbc CLK_AIB_BUS>; > > clock-names = "func", "bus"; > > + spacemit,apbc = <&syscon_apbc 0x50>; > > }; > > static int spacemit_pinctrl_probe(struct platform_device *pdev) > > { > > + struct device_node *np = pdev->dev.of_node; > > struct device *dev = &pdev->dev; > > struct spacemit_pinctrl *pctrl; > > struct clk *func_clk, *bus_clk; > > @@ -816,6 +927,18 @@ static int spacemit_pinctrl_probe(struct platform_device *pdev) > > if (IS_ERR(pctrl->regs)) > > return PTR_ERR(pctrl->regs); > > > > + pctrl->io_pd_reg = devm_platform_ioremap_resource(pdev, 1); > > + if (IS_ERR(pctrl->io_pd_reg)) > > + return PTR_ERR(pctrl->io_pd_reg); > > + > > + pctrl->regmap_apbc = > > + syscon_regmap_lookup_by_phandle_args(np, "spacemit,apbc", 1, > > + &pctrl->regmap_apbc_offset); > Can you simply use syscon_regmap_lookup_by_phandle(), then define > #define APBC_ASFAR 0x50 > #define APBC_ASSAR 0x54 I think it just a minor issue. I will keep it. But if anyone else thinks the same way as Yixun, please let me know. - Troy _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv