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[78.11.189.27]) by smtp.gmail.com with ESMTPSA id u11-20020ac243cb000000b00497ad8e6d07sm801754lfl.222.2022.09.29.07.45.27 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 29 Sep 2022 07:45:27 -0700 (PDT) Message-ID: <4ddabe3a-9f55-2a6a-c1c1-ccc3fc74e98a@linaro.org> Date: Thu, 29 Sep 2022 16:45:26 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.3.0 Subject: Re: [PATCH v1 00/30] Basic StarFive JH7110 RISC-V SoC support Content-Language: en-US To: Hal Feng , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org Cc: Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Daniel Lezcano , Thomas Gleixner , Marc Zyngier , Philipp Zabel , Stephen Boyd , Michael Turquette , Linus Walleij , Emil Renner Berthing , linux-kernel@vger.kernel.org References: <20220929143225.17907-1-hal.feng@linux.starfivetech.com> From: Krzysztof Kozlowski In-Reply-To: <20220929143225.17907-1-hal.feng@linux.starfivetech.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220929_074532_838709_F37CD241 X-CRM114-Status: GOOD ( 10.31 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On 29/09/2022 16:31, Hal Feng wrote: > This series is also available at > https://github.com/hal-feng/linux/commits/visionfive2-minimal > > [1] https://www.cnx-software.com/2022/08/23/starfive-visionfive-2-quad-core-risc-v-sbc-linux/ > [2] https://wiki.rvspace.org/ > > Emil Renner Berthing (17): > dt-bindings: riscv: Add StarFive JH7110 bindings > dt-bindings: timer: Add StarFive JH7110 clint > dt-bindings: interrupt-controller: Add StarFive JH7110 plic > dt-bindings: sifive-l2-cache: Support StarFive JH71x0 SoCs > soc: sifive: l2 cache: Convert to platform driver > soc: sifive: l2 cache: Add StarFive JH71x0 support > reset: starfive: jh7100: Use 32bit I/O on 32bit registers > dt-bindings: reset: Add StarFive JH7110 reset definitions > clk: starfive: Factor out common clock driver code > dt-bindings: clock: Add StarFive JH7110 system clock definitions > dt-bindings: clock: Add starfive,jh7110-clkgen-sys bindings > clk: starfive: Add StarFive JH7110 system clock driver > dt-bindings: clock: Add StarFive JH7110 always-on definitions > dt-bindings: clock: Add starfive,jh7110-clkgen-aon bindings > clk: starfive: Add StarFive JH7110 always-on clock driver > RISC-V: Add initial StarFive JH7110 device tree > RISC-V: Add StarFive JH7110 VisionFive2 board device tree Where is the rest of patches? Lists got only 5 of them. Anyway this is a bit too big patchset. Split per subsystem. Best regards, Krzysztof _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv