From: Ben Dooks <ben.dooks@codethink.co.uk>
To: Drew Fustini <fustini@kernel.org>
Cc: Conor Dooley <conor@kernel.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Alexandre Ghiti <alex@ghiti.fr>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Samuel Holland <samuel.holland@sifive.com>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Thomas Gleixner <tglx@linutronix.de>,
Anup Patel <anup@brainfault.org>, Arnd Bergmann <arnd@arndb.de>,
Joel Stanley <jms@tenstorrent.com>, Joel Stanley <joel@jms.id.au>,
Michael Neuling <mikey@neuling.org>,
Nicholas Piggin <npiggin@gmail.com>,
Michael Ellerman <mpe@kernel.org>, Andy Gross <agross@kernel.org>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org,
Drew Fustini <dfustini@tenstorrent.com>
Subject: Re: [PATCH 6/7] riscv: dts: Add Tenstorrent Blackhole A0 SoC PCIe cards
Date: Tue, 16 Sep 2025 19:25:59 +0100 [thread overview]
Message-ID: <51960b81-d8df-423f-b24b-4b4ec1e7a245@codethink.co.uk> (raw)
In-Reply-To: <aMmd/JQAfPwKuYyB@x1>
On 16/09/2025 18:27, Drew Fustini wrote:
> On Tue, Sep 16, 2025 at 02:56:05PM +0100, Ben Dooks wrote:
>> On 15/09/2025 18:52, Drew Fustini wrote:
>>> On Mon, Sep 15, 2025 at 05:47:08PM +0100, Conor Dooley wrote:
>>>> On Sat, Sep 13, 2025 at 02:31:05PM -0700, Drew Fustini wrote:
>>>>> new file mode 100644
>>>>> index 0000000000000000000000000000000000000000..b2b08023643a2cebd4f924579024290bb355c9b3
>>>>> --- /dev/null
>>>>> +++ b/arch/riscv/boot/dts/tenstorrent/blackhole-a0-card.dts
>>>>> @@ -0,0 +1,14 @@
>>>>> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
>>>>> +/dts-v1/;
>>>>> +
>>>>> +#include "blackhole-a0.dtsi"
>>>>> +
>>>>> +/ {
>>>>> + model = "Tenstorrent Blackhole A0 SoC PCIe card";
>>>>> + compatible = "tenstorrent,blackhole-a0-card", "tenstorrent,blackhole-a0";
>>>>> +
>>>>> + memory@0 {
>>>>> + device_type = "memory";
>>>>> + reg = <0x4000 0x30000000 0x1 0x00000000>;
>>>>
>>>> This isn't at address zero as the node address claims.
>>>
>>> Thanks, I'll fix the unit address.
>>
>> Is it time to just assume any dtc can handle a 64bit number?
>
> Is it not valid for me to use the 64 bit hex number in the unit address?
>
>
No, the reg = < > contents. It is a right pain to read split 32bit
numbers and I thought dtc had been updated to allow 64bit now?
--
Ben Dooks http://www.codethink.co.uk/
Senior Engineer Codethink - Providing Genius
https://www.codethink.co.uk/privacy.html
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next prev parent reply other threads:[~2025-09-16 18:26 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-13 21:30 [PATCH 0/7] RISC-V: Add support for Tenstorrent Blackhole SoC Drew Fustini
2025-09-13 21:31 ` [PATCH 1/7] dt-bindings: vendor-prefixes: Add Tenstorrent AI ULC Drew Fustini
2025-09-16 13:33 ` Rob Herring (Arm)
2025-09-13 21:31 ` [PATCH 2/7] dt-bindings: riscv: Add Tenstorrent Blackhole compatible Drew Fustini
2025-09-16 13:34 ` Rob Herring (Arm)
2025-09-13 21:31 ` [PATCH 3/7] dt-bindings: riscv: cpus: Add SiFive X280 compatible Drew Fustini
2025-09-16 13:37 ` Rob Herring (Arm)
2025-09-13 21:31 ` [PATCH 4/7] dt-bindings: timers: Add Tenstorrent Blackhole compatible Drew Fustini
2025-09-16 13:44 ` Rob Herring
2025-09-16 17:43 ` Drew Fustini
2025-09-13 21:31 ` [PATCH 5/7] dt-bindings: interrupt-controller: " Drew Fustini
2025-09-13 21:31 ` [PATCH 6/7] riscv: dts: Add Tenstorrent Blackhole A0 SoC PCIe cards Drew Fustini
2025-09-15 16:47 ` Conor Dooley
2025-09-15 17:52 ` Drew Fustini
2025-09-16 13:56 ` Ben Dooks
2025-09-16 17:27 ` Drew Fustini
2025-09-16 18:25 ` Ben Dooks [this message]
2025-09-13 21:31 ` [PATCH 7/7] riscv: Kconfig.socs: Add ARCH_TENSTORRENT for Tenstorrent SoCs Drew Fustini
2025-09-15 16:48 ` Conor Dooley
2025-09-15 17:52 ` Drew Fustini
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