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[108.51.35.162]) by smtp.googlemail.com with ESMTPSA id d21sm5975052qtr.45.2020.05.28.12.37.27 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 28 May 2020 12:37:27 -0700 (PDT) Subject: Re: [PATCH 5/5] dt-bindings: timer: Add CLINT bindings To: Palmer Dabbelt References: From: Sean Anderson Autocrypt: addr=seanga2@gmail.com; prefer-encrypt=mutual; keydata= mQENBFe74PkBCACoLC5Zq2gwrDcCkr+EPGsT14bsxrW07GiYzQhLCgwnPdEpgU95pXltbFhw 46GfyffABWxHKO2x+3L1S6ZxC5AiKbYXo7lpnTBYjamPWYouz+VJEVjUx9aaSEByBah5kX6a lKFZWNbXLAJh+dE1HFaMi3TQXXaInaREc+aO1F7fCa2zNE75ja+6ah8L4TPRFZ2HKQzve0/Y GXtoRw97qmnm3U36vKWT/m2AiLF619F4T1mHvlfjyd9hrVwjH5h/2rFyroXVXBZHGA9Aj8eN F2si35dWSZlIwXkNu9bXp0/pIu6FD0bI+BEkD5S7aH1G1iAcMFi5Qq2RNa041DfQSDDHABEB AAG0K1NlYW4gR2FsbGFnaGVyIEFuZGVyc29uIDxzZWFuZ2EyQGdtYWlsLmNvbT6JAVcEEwEK AEECGwMFCwkIBwIGFQgJCgsCBBYCAwECHgECF4ACGQEWIQSQYR1bzo1I0gPoYCg+6I/stKEQ bgUCXT+S2AUJB2TlXwAKCRA+6I/stKEQbhNOB/9ooea0hU9Sgh7PBloU6CgaC5mlqPLB7NTp +JkB+nh3Fqhk+qLZwzEynnuDLl6ESpVHIc0Ym1lyF4gT3DsrlGT1h0Gzw7vUwd1+ZfN0CuIx Rn861U/dAUjvbtN5kMBqOI4/5ea+0r7MACcIVnKF/wMXBD8eypHsorT2sJTzwZ6DRCNP70C5 N1ahpqqNmXe0uLdP0pu55JCqhrGw2SinkRMdWyhSxT56uNwIVHGhLTqH7Q4t1N6G1EH626qa SvIJsWlNpll6Y3AYLDw2/Spw/hqieS2PQ/Ky3rPZnvJt7/aSNYsKoFGX0yjkH67Uq8Lx0k1L w8jpXnbEPQN3A2ZJCbeMuQENBF0/k2UBCADhvSlHblNc/aRAWtCFDblCJJMN/8Sd7S9u4ZRS w1wIB4tTF7caxc8yfCHa+FjMFeVu34QPtMOvd/gfHz0mr+t0PiTAdDSbd6o7tj+g5ylm+FhT OTUtJQ6mx6L9GzMmIDEbLxJMB9RfJaL2mT5JkujKxEst6nlHGV/lEQ54xBl5ImrPvuR5Dbnr zWQYlafb1IC5ZFwSMpBeSfhS7/kGPtFY3NkpLrii/CF+ME0DYYWxlkDIycqF3fsUGGfb3HIq z2l95OB45+mCs9DrIDZXRT6mFjLcl35UzuEErNIskCl9NKlbvAMAl+gbDH275SnE44ocC4qu 0tMe7Z5jpOy6J8nNABEBAAGJATwEGAEKACYWIQSQYR1bzo1I0gPoYCg+6I/stKEQbgUCXT+T ZQIbDAUJAeEzgAAKCRA+6I/stKEQbjAGB/4mYRqZTTEFmcS+f+8zsmjt2CfWvm38kR+sJFWB vz82pFiUWbUM5xvcuOQhz698WQnIazbDGSYaOipyVNS52YiuYJDqMszzgw++DrcSuu0oRYWN EWCkJjxMqjGg8uY0OZ6FJG+gYRN5wMFErGfV1OqQ7l00FYA9OzpOEuW9PzPZEutFnAbbh77i zvxbQtT7IJCL24A4KutNYKmWg98im4mCzQcJCxE86Bv69ErLVPUyYbp4doLadScilXlvkkjL iq1wOt3rRzOuw+qnWVgWGBPxdDftz0Wck941tYF9XE0aMgkf4o1sGoDZFUFPCQdfEYPzzV7O S5hN3/mP5UeooFHb Message-ID: <51c82a3f-15d1-3c1b-9bee-d89fea706e28@gmail.com> Date: Thu, 28 May 2020 15:37:26 -0400 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.7.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200528_123731_772220_E9563C16 X-CRM114-Status: GOOD ( 18.49 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Damien Le Moal , Anup Patel , anup@brainfault.org, daniel.lezcano@linaro.org, linux-kernel@vger.kernel.org, Atish Patra , robh+dt@kernel.org, Alistair Francis , Paul Walmsley , tglx@linutronix.de, linux-riscv@lists.infradead.org, aou@eecs.berkeley.edu Sender: "linux-riscv" Errors-To: linux-riscv-bounces+infradead-linux-riscv=archiver.kernel.org@lists.infradead.org On 5/26/20 8:32 PM, Palmer Dabbelt wrote: > On Thu, 21 May 2020 23:29:36 PDT (-0700), seanga2@gmail.com wrote: >> On 5/22/20 1:54 AM, Anup Patel wrote: >>> On Fri, May 22, 2020 at 1:35 AM Sean Anderson wrote: >>>> >>>> On 5/21/20 9:45 AM, Anup Patel wrote: >>>>> +Required properties: >>>>> +- compatible : "sifive,clint-1.0.0" and a string identifying the actual >>>>> + detailed implementation in case that specific bugs need to be worked around. >>>> >>>> Should the "riscv,clint0" compatible string be documented here? This >>> >>> Yes, I forgot to add this compatible string. I will add in v2. >>> >>>> peripheral is not really specific to sifive, as it is present in most >>>> rocket-chip cores. >>> >>> I agree that CLINT is present in a lot of non-SiFive RISC-V SOCs and >>> FPGAs but this IP is only documented as part of SiFive FU540 SOC. >>> (Refer, https://static.dev.sifive.com/FU540-C000-v1.0.pdf) >>> >>> The RISC-V foundation should host the CLINT spec independently >>> under https://github.com/riscv and make CLINT spec totally open. >>> >>> For now, I have documented it just like PLIC DT bindings found at: >>> Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.txt >> >> The PLIC seems to have its own RISC-V-sponsored documentation [1] which >> was split off from the older privileged specs. By your logic above, >> should it be renamed to riscv,plic0.txt (with a corresponding change in >> the documented compatible strings)? >> >> [1] https://github.com/riscv/riscv-plic-spec > > Let's propose tagging that PLIC spec as v1.0.0 in the platform spec group, but > I don't see a reason why that wouldn't be viable. Assuming that's all OK, we > can start calling this a RISC-V PLIC (in addition to a SiFive PLIC, as they'll > be compatible). Is there a version anyewhere in that spec? I looked around a bit and couldn't find one. >>> >>> If RISC-V maintainers agree then I will document it as "RISC-V CLINT". >>> >>> @Palmer ?? @Paul ?? > > The CLINT is a SiFive spec. It has open source RTL so it's been implemented in > other designs, but it's not a RISC-V spec. The CLIC, which is a superset of > the CLINT, is a RISC-V spec. IIRC it's not finished yet (it's the fast > interrupts task group), but presumably we should have a "riscv,clic-2.0.0" (or > whatever it ends up being called) compat string to go along with the > specification. The rocket chip is a Chips Alliance project on github; presumably the "proper" compatibility string would be something like "chips-alliance,clint"? Alternatively, it is already referred to as "riscv,clint0" in U-Boot, following the pattern of the plic. --Sean