From: "Rémi Denis-Courmont" <remi@remlab.net>
To: linux-riscv@lists.infradead.org
Cc: LKML <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH -next v20 20/26] riscv: Add prctl controls for userspace vector management
Date: Sun, 21 May 2023 08:38:12 +0300 [thread overview]
Message-ID: <5677700.DvuYhMxLoT@basile.remlab.net> (raw)
In-Reply-To: <20230518161949.11203-21-andy.chiu@sifive.com>
Hi all,
Le torstaina 18. toukokuuta 2023 19.19.43 EEST, vous avez écrit :
> This patch add two riscv-specific prctls, to allow usespace control the
> use of vector unit:
>
> * PR_RISCV_V_SET_CONTROL: control the permission to use Vector at next,
> or all following execve for a thread. Turning off a thread's Vector
> live is not possible since libraries may have registered ifunc that
> may execute Vector instructions.
> * PR_RISCV_V_GET_CONTROL: get the same permission setting for the
> current thread, and the setting for following execve(s).
So far the story was that if the nth bit in the ELF HWCAP auxillary vector was
set, then the nth single lettered extension was supported. There is already
userspace code out there that expects this of the V bit. (I know I have
written such code, and I also know others did likewise.) This is how it
already works for the D and F bits.
Admittedly, upstream Linux has never ever set that bit to this day. But still,
if we end up with the bit set in a process that has had V support disabled by
the parent (or the sysctl), existing userspace will encounter SIGILL and
break.
IMO, the bit must be masked not only whence the kernel lacks V support (as
PATCH 02 does), but also if the process starts with V disabled.
There are two ways to achieve this:
1) V is never ever set, and userspace is forced to use hwprobe() instead.
2) V is set only in processes starting with V enabled (and it's their own
fault if they disabled it in future child threads).
Br,
--
レミ・デニ-クールモン
http://www.remlab.net/
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next prev parent reply other threads:[~2023-05-21 5:38 UTC|newest]
Thread overview: 57+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-18 16:19 [PATCH -next v20 00/26] riscv: Add vector ISA support Andy Chiu
2023-05-18 16:19 ` [PATCH -next v20 01/26] riscv: Rename __switch_to_aux() -> fpu Andy Chiu
2023-05-18 16:19 ` [PATCH -next v20 02/26] riscv: Extending cpufeature.c to detect V-extension Andy Chiu
2023-05-18 16:19 ` [PATCH -next v20 03/26] riscv: hwprobe: Add support for probing V in RISCV_HWPROBE_KEY_IMA_EXT_0 Andy Chiu
2023-05-18 17:28 ` Conor Dooley
2023-05-19 16:50 ` Evan Green
2023-05-24 0:48 ` Palmer Dabbelt
2023-06-01 4:46 ` Guo Ren
2023-05-18 16:19 ` [PATCH -next v20 04/26] riscv: Add new csr defines related to vector extension Andy Chiu
2023-05-18 16:19 ` [PATCH -next v20 05/26] riscv: Clear vector regfile on bootup Andy Chiu
2023-05-18 16:19 ` [PATCH -next v20 06/26] riscv: Disable Vector Instructions for kernel itself Andy Chiu
2023-05-18 16:19 ` [PATCH -next v20 07/26] riscv: Introduce Vector enable/disable helpers Andy Chiu
2023-05-18 16:19 ` [PATCH -next v20 08/26] riscv: Introduce riscv_v_vsize to record size of Vector context Andy Chiu
2023-05-18 16:19 ` [PATCH -next v20 09/26] riscv: Introduce struct/helpers to save/restore per-task Vector state Andy Chiu
2023-05-24 0:49 ` Palmer Dabbelt
2023-05-18 16:19 ` [PATCH -next v20 10/26] riscv: Add task switch support for vector Andy Chiu
2023-05-24 0:49 ` Palmer Dabbelt
2023-05-30 10:11 ` Andy Chiu
2023-05-18 16:19 ` [PATCH -next v20 11/26] riscv: Allocate user's vector context in the first-use trap Andy Chiu
2023-05-18 17:47 ` Conor Dooley
2023-05-22 9:40 ` Andy Chiu
2023-05-24 0:49 ` Palmer Dabbelt
2023-05-24 14:21 ` Darius Rad
2023-05-30 16:51 ` Guo Ren
2023-05-18 16:19 ` [PATCH -next v20 12/26] riscv: Add ptrace vector support Andy Chiu
2023-05-24 0:49 ` Palmer Dabbelt
2023-05-24 6:32 ` Arnd Bergmann
2023-05-24 7:50 ` Andreas Schwab
2023-05-18 16:19 ` [PATCH -next v20 13/26] riscv: signal: check fp-reserved words unconditionally Andy Chiu
2023-05-18 16:19 ` [PATCH -next v20 14/26] riscv: signal: Add sigcontext save/restore for vector Andy Chiu
2023-05-18 16:19 ` [PATCH -next v20 15/26] riscv: signal: Report signal frame size to userspace via auxv Andy Chiu
2023-05-18 16:19 ` [PATCH -next v20 16/26] riscv: signal: validate altstack to reflect Vector Andy Chiu
2023-05-18 16:19 ` [PATCH -next v20 17/26] riscv: prevent stack corruption by reserving task_pt_regs(p) early Andy Chiu
2023-05-18 16:19 ` [PATCH -next v20 18/26] riscv: kvm: Add V extension to KVM ISA Andy Chiu
2023-05-18 16:19 ` [PATCH -next v20 19/26] riscv: KVM: Add vector lazy save/restore support Andy Chiu
2023-05-18 16:19 ` [PATCH -next v20 20/26] riscv: Add prctl controls for userspace vector management Andy Chiu
2023-05-20 14:11 ` kernel test robot
2023-05-21 1:50 ` kernel test robot
2023-05-21 5:38 ` Rémi Denis-Courmont [this message]
2023-05-22 8:28 ` Andy Chiu
2023-05-23 13:56 ` Björn Töpel
2023-05-18 16:19 ` [PATCH -next v20 21/26] riscv: Add sysctl to set the default vector rule for new processes Andy Chiu
2023-05-23 13:45 ` Björn Töpel
2023-05-18 16:19 ` [PATCH -next v20 22/26] riscv: detect assembler support for .option arch Andy Chiu
2023-05-18 16:19 ` [PATCH -next v20 23/26] riscv: Enable Vector code to be built Andy Chiu
2023-05-18 17:31 ` Conor Dooley
2023-05-24 0:22 ` Palmer Dabbelt
2023-05-18 16:19 ` [PATCH -next v20 24/26] riscv: Add documentation for Vector Andy Chiu
2023-05-19 8:09 ` Bagas Sanjaya
2023-05-21 5:20 ` Rémi Denis-Courmont
2023-05-18 16:19 ` [PATCH -next v20 25/26] selftests: Test RISC-V Vector prctl interface Andy Chiu
2023-05-18 16:19 ` [PATCH -next v20 26/26] selftests: add .gitignore file for RISC-V hwprobe Andy Chiu
[not found] <2760633E-0DFA-4A72-AF4A-21613BEBA55D@remlab.net>
2023-05-24 0:18 ` [PATCH -next v20 20/26] riscv: Add prctl controls for userspace vector management Palmer Dabbelt
2023-05-24 9:25 ` Andy Chiu
2023-05-24 16:16 ` Rémi Denis-Courmont
2023-05-30 14:14 ` Andy Chiu
2023-05-24 16:13 ` Rémi Denis-Courmont
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