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X-CSE-ConnectionGUID: sk0ZVqhpQpa/1fIFSwhulg== X-CSE-MsgGUID: DPLQCEKTSJ6+G0Gc+1PYNQ== X-IronPort-AV: E=McAfee;i="6700,10204,11138"; a="22767598" X-IronPort-AV: E=Sophos;i="6.09,220,1716274800"; d="scan'208";a="22767598" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Jul 2024 06:26:55 -0700 X-CSE-ConnectionGUID: 0qsrKouuQIymE30/DFvR0A== X-CSE-MsgGUID: v4XoAXGgTjuJS6tBlKSl7w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,220,1716274800"; d="scan'208";a="50800301" Received: from ahunter6-mobl1.ger.corp.intel.com (HELO [10.0.2.15]) ([10.245.150.149]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Jul 2024 06:26:48 -0700 Message-ID: <5e79be33-e914-4eb6-b8c4-a18b3c5dfcf7@intel.com> Date: Fri, 19 Jul 2024 16:26:40 +0300 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 5/8] mmc: sdhci-of-dwcmshc: add dwcmshc_pltfm_data To: Chen Wang , aou@eecs.berkeley.edu, conor+dt@kernel.org, guoren@kernel.org, inochiama@outlook.com, jszhang@kernel.org, krzysztof.kozlowski+dt@linaro.org, palmer@dabbelt.com, paul.walmsley@sifive.com, robh@kernel.org, ulf.hansson@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-riscv@lists.infradead.org, chao.wei@sophgo.com, haijiao.liu@sophgo.com, xiaoguang.xing@sophgo.com, tingzhu.wang@sophgo.com Cc: Chen Wang References: <63b66e64c22b5ef73df2d0aa2f5a992d562898d8.1721377374.git.unicorn_wang@outlook.com> Content-Language: en-US From: Adrian Hunter Organization: Intel Finland Oy, Registered Address: PL 281, 00181 Helsinki, Business Identity Code: 0357606 - 4, Domiciled in Helsinki In-Reply-To: <63b66e64c22b5ef73df2d0aa2f5a992d562898d8.1721377374.git.unicorn_wang@outlook.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240719_062656_372626_E6FCAAAF X-CRM114-Status: GOOD ( 17.86 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On 19/07/24 11:46, Chen Wang wrote: > From: Chen Wang > > Abstract dwcmshc_pltfm_data to hold the sdhci_pltfm_data > plus some comoon operations of soc such as init/postinit. > > Signed-off-by: Chen Wang > --- > drivers/mmc/host/sdhci-of-dwcmshc.c | 83 +++++++++++++++++------------ > 1 file changed, 50 insertions(+), 33 deletions(-) > > diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c > index 30e4cea8a058..972d03ec60e3 100644 > --- a/drivers/mmc/host/sdhci-of-dwcmshc.c > +++ b/drivers/mmc/host/sdhci-of-dwcmshc.c > @@ -205,6 +205,8 @@ struct rk35xx_priv { > > #define DWCMSHC_MAX_OTHER_CLKS 3 > > +struct dwcmshc_pltfm_data; Forward declaration not needed > + > struct dwcmshc_priv { > struct clk *bus_clk; > int vendor_specific_area1; /* P_VENDOR_SPECIFIC_AREA1 reg */ > @@ -218,6 +220,12 @@ struct dwcmshc_priv { > u16 flags; > }; > > +struct dwcmshc_pltfm_data { > + const struct sdhci_pltfm_data pdata; > + int (*init)(struct device *dev, struct sdhci_host *host, struct dwcmshc_priv *dwc_priv); > + void (*postinit)(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv); > +}; > + > static int dwcmshc_get_enable_other_clks(struct device *dev, > struct dwcmshc_priv *priv, > int num_clks, > @@ -1048,39 +1056,52 @@ static const struct sdhci_ops sdhci_dwcmshc_cv18xx_ops = { > .platform_execute_tuning = cv18xx_sdhci_execute_tuning, > }; > > -static const struct sdhci_pltfm_data sdhci_dwcmshc_pdata = { > - .ops = &sdhci_dwcmshc_ops, > - .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, > - .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, > +static const struct dwcmshc_pltfm_data sdhci_dwcmshc_pdata = { > + .pdata = { > + .ops = &sdhci_dwcmshc_ops, > + .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, > + .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, > + }, > }; > > #ifdef CONFIG_ACPI > -static const struct sdhci_pltfm_data sdhci_dwcmshc_bf3_pdata = { > - .ops = &sdhci_dwcmshc_ops, > - .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, > - .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | > - SDHCI_QUIRK2_ACMD23_BROKEN, > +static const struct dwcmshc_pltfm_data sdhci_dwcmshc_bf3_pdata = { > + .pdata = { > + .ops = &sdhci_dwcmshc_ops, > + .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, > + .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | > + SDHCI_QUIRK2_ACMD23_BROKEN, > + }, > }; > #endif > > -static const struct sdhci_pltfm_data sdhci_dwcmshc_rk35xx_pdata = { > - .ops = &sdhci_dwcmshc_rk35xx_ops, > - .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN | > - SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, > - .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | > - SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN, > +static const struct dwcmshc_pltfm_data sdhci_dwcmshc_rk35xx_pdata = { > + .pdata = { > + .ops = &sdhci_dwcmshc_rk35xx_ops, > + .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN | > + SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, > + .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | > + SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN, > + }, > + .init = dwcmshc_rk35xx_init, > + .postinit = dwcmshc_rk35xx_postinit, > }; > > -static const struct sdhci_pltfm_data sdhci_dwcmshc_th1520_pdata = { > - .ops = &sdhci_dwcmshc_th1520_ops, > - .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, > - .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, > +static const struct dwcmshc_pltfm_data sdhci_dwcmshc_th1520_pdata = { > + .pdata = { > + .ops = &sdhci_dwcmshc_th1520_ops, > + .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, > + .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, > + }, > + .init = th1520_init, > }; > > -static const struct sdhci_pltfm_data sdhci_dwcmshc_cv18xx_pdata = { > - .ops = &sdhci_dwcmshc_cv18xx_ops, > - .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, > - .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, > +static const struct dwcmshc_pltfm_data sdhci_dwcmshc_cv18xx_pdata = { > + .pdata = { > + .ops = &sdhci_dwcmshc_cv18xx_ops, > + .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, > + .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, > + }, > }; > > static const struct cqhci_host_ops dwcmshc_cqhci_ops = { > @@ -1196,7 +1217,7 @@ static int dwcmshc_probe(struct platform_device *pdev) > struct sdhci_pltfm_host *pltfm_host; > struct sdhci_host *host; > struct dwcmshc_priv *priv; > - const struct sdhci_pltfm_data *pltfm_data; > + const struct dwcmshc_pltfm_data *pltfm_data; > int err; > u32 extra, caps; > > @@ -1206,7 +1227,7 @@ static int dwcmshc_probe(struct platform_device *pdev) > return -ENODEV; > } > > - host = sdhci_pltfm_init(pdev, pltfm_data, > + host = sdhci_pltfm_init(pdev, &pltfm_data->pdata, > sizeof(struct dwcmshc_priv)); > if (IS_ERR(host)) > return PTR_ERR(host); > @@ -1251,16 +1272,12 @@ static int dwcmshc_probe(struct platform_device *pdev) > host->mmc_host_ops.hs400_enhanced_strobe = dwcmshc_hs400_enhanced_strobe; > host->mmc_host_ops.execute_tuning = dwcmshc_execute_tuning; > > - if (pltfm_data == &sdhci_dwcmshc_rk35xx_pdata) { > - err = dwcmshc_rk35xx_init(dev, host, priv); > + if (pltfm_data->init) { > + err = pltfm_data->init(&pdev->dev, host, priv); > if (err) > goto err_clk; > } > > - if (pltfm_data == &sdhci_dwcmshc_th1520_pdata) { > - th1520_init(dev, host, priv); > - } > - > #ifdef CONFIG_ACPI > if (pltfm_data == &sdhci_dwcmshc_bf3_pdata) > sdhci_enable_v4_mode(host); > @@ -1288,8 +1305,8 @@ static int dwcmshc_probe(struct platform_device *pdev) > dwcmshc_cqhci_init(host, pdev); > } > > - if (priv->priv) > - dwcmshc_rk35xx_postinit(host, priv); > + if (pltfm_data->postinit) > + pltfm_data->postinit(host, priv); > > err = __sdhci_add_host(host); > if (err) _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv