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([2601:600:9001:ecb0::9267]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-71908fc8506sm4612609b3a.5.2024.09.12.06.48.30 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 12 Sep 2024 06:48:30 -0700 (PDT) Message-ID: <605c618c-e044-457a-abd4-66db43999e64@rivosinc.com> Date: Thu, 12 Sep 2024 06:48:29 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] drivers/perf: riscv: Align errno for unsupported perf event To: Pu Lehui , linux-riscv@lists.infradead.org Cc: Atish Patra , Anup Patel , Palmer Dabbelt , =?UTF-8?B?QmrDtnJuIFTDtnBlbA==?= , Pu Lehui References: <20240831071520.1630360-1-pulehui@huaweicloud.com> Content-Language: en-US From: Atish Patra In-Reply-To: <20240831071520.1630360-1-pulehui@huaweicloud.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240912_064832_215074_D3E6D483 X-CRM114-Status: GOOD ( 18.26 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On 8/31/24 12:15 AM, Pu Lehui wrote: > From: Pu Lehui > > RISC-V perf driver does not yet support PERF_TYPE_BREAKPOINT. It would > be more appropriate to return -EOPNOTSUPP or -ENOENT for this type in > pmu_sbi_event_map. Considering that other implementations return -ENOENT > for unsupported perf types, let's synchronize this behavior. Due to this > reason, a riscv bpf testcases perf_skip fail. Meanwhile, align that > behavior to the rest of proper place. > > Signed-off-by: Pu Lehui > --- > drivers/perf/riscv_pmu_legacy.c | 4 ++-- > drivers/perf/riscv_pmu_sbi.c | 4 ++-- > 2 files changed, 4 insertions(+), 4 deletions(-) > > diff --git a/drivers/perf/riscv_pmu_legacy.c b/drivers/perf/riscv_pmu_legacy.c > index 04487ad7fba0..93c8e0fdb589 100644 > --- a/drivers/perf/riscv_pmu_legacy.c > +++ b/drivers/perf/riscv_pmu_legacy.c > @@ -22,13 +22,13 @@ static int pmu_legacy_ctr_get_idx(struct perf_event *event) > struct perf_event_attr *attr = &event->attr; > > if (event->attr.type != PERF_TYPE_HARDWARE) > - return -EOPNOTSUPP; > + return -ENOENT; > if (attr->config == PERF_COUNT_HW_CPU_CYCLES) > return RISCV_PMU_LEGACY_CYCLE; > else if (attr->config == PERF_COUNT_HW_INSTRUCTIONS) > return RISCV_PMU_LEGACY_INSTRET; > else > - return -EOPNOTSUPP; > + return -ENOENT; > } > > /* For legacy config & counter index are same */ > diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c > index 44d3951d009f..169c5157b916 100644 > --- a/drivers/perf/riscv_pmu_sbi.c > +++ b/drivers/perf/riscv_pmu_sbi.c > @@ -309,7 +309,7 @@ static void pmu_sbi_check_event(struct sbi_pmu_event_data *edata) > ret.value, 0x1, SBI_PMU_STOP_FLAG_RESET, 0, 0, 0); > } else if (ret.error == SBI_ERR_NOT_SUPPORTED) { > /* This event cannot be monitored by any counter */ > - edata->event_idx = -EINVAL; > + edata->event_idx = -ENOENT; > } > } > > @@ -543,7 +543,7 @@ static int pmu_sbi_event_map(struct perf_event *event, u64 *econfig) > } > break; > default: > - ret = -EINVAL; > + ret = -ENOENT; > break; > } > Lgtm. Thanks for aligning the error codes in other places. Reviewed-by: Atish Patra _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv